Qualcomm Incorporated

Kevin Stuart Cousineau

Jai N Subrahmanyam

Jinxia Bai

Chinnappa K Ganapathy

Durk L Van Veen

Michael G Matthews

Scott C Asbill

Seokyong Oh

Michael Mao Wang

Raghuraman Krishnamoorthi

Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

IFFT processing in wireless communications

Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.

The present invention provides devices for controlling a desired output of an output device. These devices include a first conductor, a second conductor having a varying, predetermined spacing from the first conductor, and a third conductor positioned on the actuator mechanism and having a plurality of interconnecting positions between the first conductor and the second conductor. A predetermined one of a plurality of output signals may be produced when the third conductor connects the first conductor and the second conductor to control the desired output of the output device.

Signal-producing mechanism

An FFT engine implementing a cycle count method of applying twiddle multiplications in multi-stages. When implementing a multistage FFT, the intermediate values need to be multiplied by various twiddle factors. The FFT engine utilizes a minimal number of multipliers to perform the twiddle multiplications in an efficient pipeline. Optimizing a number of complex multipliers based on an FFT radix and a number of values in each row of memory allows the FFT function to be performed using a reasonable amount of area and in a minimal number of cycles. Strategic ordering and grouping of the values allows the FFT operation to be performed in a fewer number of cycles.

Fast Fourier transform twiddle multiplication

An FFT processor for an OFDM receiver includes multiple interrelated operational blocks. The FFT processor is configured to perform data demodulation, channel estimation, and fine timing acquisition on received OFDM symbols. The FFT processor incorporates a pipelined FFT engine using a memory architecture shared with channel estimation and demodulation blocks. The combination of the shared memory structure and the pipelined FFT operation enable the channel estimation and demodulation processing to be completed during the time used to capture the next received symbol.

Fast fourier transform processing in an OFDM system

Apparatus and methods of determining a modulo count of a synchronization number in a sleep capable system. The synchronization number is stored in a comparison register, and a comparison number equal to the largest power of two multiple of the modulus within a predetermined range is subtracted from the synchronization number. If the difference is zero, the difference is stored in the comparison register, replacing the previous number stored in the register. If the difference is less than zero, the number stored in the register remains unchanged. The comparison number is right shifted, resulting in division by two. The process is repeated for a number of loops equal to the power of two, or until the difference is less than the modulus.

Determining modulo count in sleep capable system

In an OFDM system, multiple (M) interlaces are defined for M non-overlapping sets of frequency subbands, and M slots with fixed indices are also defined. Data streams and pilot are mapped to slots, which are in turn mapped to interlaces based on a slot-to-interlace mapping scheme that can achieve frequency diversity and good performance for all slots. At a transmitter, a slot-to-interlace converter maps the slots to the interlaces. The slot-to-interlace converter includes multiple multiplexers and a control unit. The multiplexers map the M slots to the M interlaces based on the slot-to-interlace mapping scheme. The control unit generates at least one control signal for the multiplexers. The multiplexers may be arranged and controlled in various manners depending on the slot-to-interlace mapping scheme. At a receiver, a complementary interlace-to-slot converter maps the interlaces to the slots.

Slot-to-interlace and interlace-to-slot converters for an OFDM system

The present invention provides systems, devices and methods for controlling a desired output of an output device. These systems, devices and methods include connecting an electrical resistance element having a selected one of a plurality of resistance values with an electrical circuit portion having a plurality of electrical components, determining an electrical characteristic associated with the connected electrical circuit portion and the variable resistance element, and generating a control signal based on the electrical characteristic to control the desired output of the output device.

Control systems

A re-synchronizing phase-independent first-in first-out (FIFO) memory aligns digital data transmitted between receive shelves and digital shelves in the gateway transceiver subsystem (GTS) of a low orbit (LEO) satellite system. RF data transmitted from an LEO satellite is segmented into multiple receive shelves designed to filter and sample a large volume of information. The receive shelves filter the data, down convert the data to an IF frequency range and clock the data into the digital shelves, where demodulator ASICs demodulate the data to retrieve an original signal sent by a mobile radio-telephone user. The resynchronizing phase-independent FIFO memory uses separate input clock (CLK_IN) signals and input synchronization (EVEN_SEC) signals to align data leaving the receive shelves. It also uses an independent timed output clock (CLK_OUT) signal and an independent output synchronization (SYNC_OUT) signal to align the same data as it goes into the digital shelves. This prevents the isochronous (same frequency) signals from being phase misaligned due to disadvantageous Doppler effects or component characteristics.

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Ramona, CA, United States of America

Kevin Stuart Cousineau