International Business Machines Corporation

Kevin Shawn Petrarca

Richard Paul Volant

Mukta G Farooq

Lawrence Alfred Clevenger

Kenneth Jay Stein

Carl John Radens

Timothy Joseph Dalton

George Frederick Walker

Donald Francis Canaperi

Kaushik Arun Kumar

Jeffrey P Gambino

John Michael Cotte

Mahadevaiyer Krishnan

Rebecca D Mih

Daniel C Edelstein

Sampath Purushothaman

Christopher Vincent Jahnes

Roger Allan Quon

Ian D Melville

John Harold Magerlein

Robert Allen Groves

Shahab Siddiqui

Stephan Grunow

Seshadri Subbanna

Wolfgang Sauter

Zhengwen O Li

Satyanarayana Venkata Nitta

Chandrasekhar Narayan

Carlos Juan Sambucetti

Rainer Klaus Krause

Tien-Jen Cheng

Stuart A Sieg

Harold John Hovel

Kevin M Prettyman

Anthony K Stamper

Shom Ponoth

Hariklia Deligianni

Katherine Lynn Saenger

Vincent James McGahay

Tom C Lee

Vidhya Ramachandran

Panayotis Constantinou Andricacos

Michael Straight Hibbs

Sarah Huffsmith Knickerbocker

William Francis Landers

Stanley Joseph Whitehair

Steven Erik Steen

Kangguo Cheng

Ruilong Xie

Theodorus E Standaert

Alfred Grill

Douglas Duane Coolbaugh

Kenneth Parker Rodbell

Stephen McConnell Gates

Peter Alfred Gruber

Andrew Herbert Simon

Laertis Economikos

Wayne Martin Moreau

Christos Dimitrios Dimitrakopoulos

Jeffrey Curtis Hedrick

Johnathan E Faltermeier

Ebenezer E Eshun

Takashi Hisada

Robert Hannon

Kenneth John McCullough

John Patrick Simons

Charles Jesse Taft

Kamalesh K Srivastava

Ira L Allen

Troy Lawrence Graves-Abe

Randolph F Knarr

Ricardo Alves Donaton

Habib Hichri

Ramachandra Divakaruni

Kevin K Chan

Timothy Harrison Daubenspeck

Zhong-Xiang He

Christopher David Muzzy

Qinghuang Lin

Subramanian Srikanteswara Iyer

David William Abraham

Russell Alan Budd

Kisik Choi

Griselda Bonilla

Katsuyuki Sakuma

Fen Chen

Emily R Kinser

Douglas Max Gill

Bruce Kenneth Furman

James L Speidell

Cornelia K Tsang

James Gardner Ryan

Raymond R Horton

Vivekananda P Adiga

Maheswaran Surendra

Nancy Anne Greco

Kevin R Winstel

Somnath Ghosh

Nicholas A Polomoff

Kelly Malone

A semiconductor device includes a first buried power rail (BPR) disposed through etch stop layers and a second BPR disposed in direct contact with the first BPR, where the first BPR has a larger critical dimension (CD) than the second BPR. A bottom surface of the first BPR directly contacts a via-to buried power rail (VBPR) contact. Source/drain contacts (CA) are disposed adjacent the VBPR contact and source/drain regions collectively defining middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed adjacent to the MOL components, and the MOL and BEOL components bond to a carrier wafer. The second BPR is then constructed on the carrier wafer.

Buried power rail at tight cell-to-cell space

A semiconductor structure is provided in which a via to buried power rail (VBPR) contact structure is present that has a via portion contacting a buried power rail and a non-via portion contacting a source/drain region of a first functional gate structure present in a first device region. A dielectric spacer structure including a base dielectric spacer and a replacement dielectric spacer is located between the VPBR contact structure and the first functional gate structure. The replacement dielectric spacer is composed of a gate cut trench dielectric material that is also present in a gate cut trench that is located between the first functional gate structure present in the first device region, and a second functional gate structure that is present in a second device region. The replacement dielectric spacer replaces a damaged region of a dielectric spacer that is originally present during VBPR formation.

Structure containing a via-to-buried power rail contact structure or a via-to-backside power rail contact structure

The subject disclosure is directed towards layered substrate structures with aligned optical access to electrical devices formed thereon for laser processing and electrical device tuning. According to an embodiment, a layered substrate structure is provided that comprises an optical substrate having a first surface and a second surface and a patterned bonding layer formed on the second surface that comprises a bonding region and an open region, wherein the open region exposes a portion of the second surface. The layered substrate structure further comprises a device chip bonded to the patterned bonding layer via the bonding region and comprising at least one electrical component aligned with the optical substrate and the open region. The at least one electrical component can include for example, a thin film wire, an air bridge, a qubit, an electrode, a capacitor or a resonator.

Layered substrate structures with aligned optical access to electrical devices

A semiconductor device comprises a first chip layer, having a first chip layer front-side and a first chip layer back-side, a qubit chip layer, having a qubit chip layer front-side and a qubit chip layer back-side, the qubit chip layer front-side operatively coupled to the first chip layer front-side with a set of bump-bonds, a set of through-silicon vias (TSVs) connected to at least one of: the first chip layer back-side or the qubit chip layer back-side and a cap wafer metal bonded to at least one of: the qubit chip layer back-side or the first chip layer back-side.

Create a protected layer for interconnects and devices in a packaged quantum structure

Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Ionizing radiation blocking in IC chip to reduce soft errors

Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.

Insulating a via in a semiconductor substrate

Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.

Flip chip alignment mark exposing method enabling wafer level underfill

Method for forming a through semiconductor via (TSV) in a semiconductor wafer comprising: etching an annular recess into a front side of the semiconductor wafer, the annular recess surrounding a pillar of the semiconductor material; filling the annular recess with an insulative material to form an insulative annulus; etching a recess into the front side in the pillar of the semiconductor material; filling the recess in the portion of the semiconductor material with a metal to form a through semiconductor via (TSV); thinning the semiconductor wafer from a backside of the semiconductor wafer and stopping on the insulative annulus to expose the pillar of the semiconductor material; recessing the pillar of the semiconductor material from the back side to form a recess that exposes an end of the TSV; and filling the recess with a metal to a level at least even with a level of the insulative annulus.

Protected through semiconductor via (TSV)

Method and apparatus to provide a self-locking container to prevent unwanted access to materials stored in the container as a result of exposure to conditions that compromise the effectiveness or safety of the materials. A container may be threaded to receive a threaded lid, and the container may comprise a bolt movable within a channel from a retracted position, which allows the lid to be threadably connected or removed, to a locked position, which prevents removal of the lid. The bolt is movable to the locked position by a drive member, such as a bimetallic strip or a shape-memory element that drive the bolt in response to exposure to the condition that compromises the material.

Self-locking container

A semiconductor structure having a through semiconductor via (TSV) which includes a semiconductor wafer of a semiconductor material and having a front side and a back side; front end of the line (FEOL) components; an insulative annulus extending from the front side to the back side, the insulative annulus having a center including the semiconductor material such that the semiconductor material in the center of the insulative annulus is recessed from the back side to form a recess; a metal filling the recess; a through silicon via (TSV) extending in a straight line from the metal-filled recess, through the center of the semiconductor material in the center of the insulative annulus and into the FEOL components such that there is semiconductor material between the TSV and the insulative annulus.

A trench isolation structure is formed beneath a topmost surface of a semiconductor substrate. A mandrel structure having a bottommost surface that straddles a sidewall edge of the underlying trench isolation structure is then formed. Nitride spacers are formed on sidewalls of the mandrel structure and thereafter the mandrel structure is removed. A dielectric oxide material is then formed having a topmost surface that is coplanar with a topmost surface of each remaining nitride spacer. Each nitride spacer is removed and thereafter a semiconductor fin is epitaxially grown within a cavity in the dielectric oxide material which exposes a topmost surface of the semiconductor substrate.

Selectively grown self-aligned fins for deep isolation integration

Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure

Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.

Enhanced capture pads for through semiconductor vias

In a method for controlling pricing of a product, a radio frequency identification (RFID) tag having at least one processor is attached to a monitored product. A value indicative of a degree of exposure to an environmental condition is obtained. The obtained value is compared with a predetermined value range. A price of the monitored product is adjusted when the result of the comparison falls outside the predetermined value range.

RFID tag with environmental sensor

Growing community of inventors

Newburgh, NY, United States of America

Kevin Shawn Petrarca