Hewlett-packard Development Company, L.p.

Intel Corporation

Kevin Safford

Patrick Knebel

Russell C Brockmann

Jeremy Petsinger

Rohit Bhatia

Donald Charles Soltis, Jr

Karl P Brummel

Eric R Delano

Stephen R Undy

Joel D Lamb

Blaine Stackhouse

Chris Bostak

Steve Undy

Richard Blumberg

Tsvika Kurts

Bruce A Long

Larisa Novakovsky

Yoni Aizik

Hisham Shafi

Peter Lachner

Ronny Lee Arnold

Michael Paulitsch

Hermann Gartler

Riccardo Mariani

Chris Poirier

Cameron B McNairy

Benjamin James Patella

Boris Dolgunov

Michael J St Clair

Ki W Yoon

Mark M Gibson

Christopher L Lyles

William Penner

Marcus R Winston

Susith Rohana Fernando

Anuj Dua

Victor Ruybalid

Loren James McConnell

Robert E Weidner

Vamsi Krishna Jakkampudi

Vinothkumar V Ethiraj

Jane Wang

M A Susith Rohana Fernando

Riccardo Locatelli

Embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. A routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. The control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. Otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. Other embodiments may also be described and claimed.

Routing traffics having primary and secondary destinations in communication networks

Methods and apparatus for protecting trace data of a remote debug session for a computing system. In one embodiment, a method includes storing trace data received from one or more trace interfaces to a storage location of a target device, where the trace data is generated from execution at the target device, and where the trace data is protected from an unauthorized access. The method continues with transmitting the trace data to a debug host computer with encryption through a communication channel between the target device and the debug host computer.

Method and apparatus for protecting trace data of a remote debug session

A system to evaluate functional safety in an integrated circuit. The system includes a first circuit to execute an operation to cause to system to perform a function, where the function associated with a specified safety integrity level. The system also includes second circuit to capture trace data at an interface to the first circuit or at internal signals without inhibiting performance of the function, where the trace data comprising information that is used to determine whether the system can perform the function with an indicated level of functional safety and transmit the trace data to a safety evaluation circuit.

Functional safety over trace-and-debug

Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

Supporting hang detection and data recovery in microprocessor systems

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using PSMI using at-speed scan capture. For example, in one embodiment, such a system includes an input signal capture device to capture input signals input to a silicon processor under test; a scan capture device to capture a scan snapshot representing a known state of a plurality of digital elements integrated within the silicon processor under test, each having state data for the silicon processor under test; a scan read-out device to communicate the captured scan snapshot to a storage point physically external from the silicon processor under test; and a model of the silicon processor under test to replay a subset of a test sequence for the silicon processor under test based at least in part on the captured input signals and the captured scan snapshot.

PSMI using at-speed scan capture

Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

Methods and apparatuses for reducing step loads of processors

A method and apparatus for discovering errors in a translation look-aside buffer (TLB). The TLB comprises a content addressable memory (CAM) and a random access memory (RAM). The TLB contains additional logic to check for error when the TLB is not in normal use to translate from a first set of elements, stored as entries in the CAM, to a second set of elements, stored as entries in the RAM. If the TLB is not in normal use, a RAM entry is selected and checked for errors. If an error is detected in the RAM entry, the corresponding TLB entry is purged.

Method and apparatus to search for errors in a translation look-aside buffer

An apparatus for communicating between lock step is incorporated on two or more processors operating in a lock step mode. Each of the processors includes processor logic to execute a code sequence, and an identical code sequence is executed by the processor logic. The apparatus further includes a processor-specific resource referenced by the code sequence. A multiplexer is coupled to the processor-specific resource, and is controlled to read data based on the identification. Coupled to the processors is a lock step logic block operable to read and compare the output of each of the processors. The lock step logic determines if operation of the processors is in a lock step mode or in an independent processor mode. Such determination may be made by the lock step logic turning off, for example.

Method and apparatus for communicating information between lock stepped processors

The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.

System and method for responding to TLB misses

An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode. Each of the two or more processors comprise a processor-specific resource operable to seed the differences, a processor logic to execute a code sequence, in which an identical code sequence is executed by the processor logic of each of the two or more processors, and an output to provide a result of execution of the code sequence. The processor outputs, based on execution of the code sequence is provided to a lock step logic operable to read and compare the output of each of the two or more processors.

Method and apparatus for seeding differences in lock-stepped processors

An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operating in the computer system, each of the processor units having at least two processor units operating in lock step, and at least one idle processor unit operating in lock step; and a controller coupled to the two processor units operating in lock step and the idle processor unit. The controller includes mechanisms for copying an architected state of each of the two lock step processor units to the idle processor unit.

Method and apparatus for recovery from loss of lock step

The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexer or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.

Method and apparatus for implementing two architectures in a chip

Techniques are disclosed, for use in a computer system including a plurality of processing units coupled over a system fabric, to identify a lockstep error associated with a first packet to be transmitted over the system fabric; set a viral indicator in the first packet to indicate the lockstep error; and transmit the modified packet over the system fabric.

Lockstep error signaling

Growing community of inventors

Fort Collins, CO, United States of America

Kevin Safford