Rambus Inc.

Other

Kevin S Donnelly

Jared L Zerbe

Mark A Horowitz

Bruno Werner Garlepp

Craig Edward Hampel

Alfredo Moncayo

Richard Maurice Barth

Stefanos Sidiropoulos

Pak Shing Chau

Donald C Stark

Tsyr-Chyang Ho

Jun Y Kim

Leung Yu

Thomas H Lee

Mark G Johnson

Roxanne T Vu

Ely K Tsern

Chanh Vi Tran

Benedict Chung-Kwong Lau

Brian S Leibowitz

John Wood Poulton

Fred F Chen

Billy Wayne Garrett, Jr

Ramin Farjad-Rad

Donald Victor Perino

Clemenz L Portmann

Carl William Werner

Andrew P Ho

Frederick Abbott Ware

Gary Bela Bronner

Haw-Jyh Liaw

Benedict C Lau

Paul G Davis

Nhat M Nguyen

Yiu-Fai Chan

Brent Steven Haukness

Nancy David Dillon, Legal Representative

Vladimir Marko Stojanovic

James A Gasbarro

John Bradly Dillon

Mark D Kellam

Andrew C Ho

Fredrick A Ware

Srinivas Nimmagadda

Jeffrey D Mitchell

Ming Chu Li

Yohan Usthavia Frans

Kun-Yung Chang

Jason C Wei

Todd W Bystrom

Donald R Mullen

Dennis Kim

Ian P Shaeffer

Wayne S Richardson

Chaofeng Huang

Grace Tsang

Michael T Ching

Wendemagegnehu Beyene

Andy Chan

Ralph H Donnelly

Brian Lebowitz

Billy W Garrett

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

High-speed signaling systems with adaptable pre-emphasis and equalization

An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Flash controller to provide a value that represents a parameter to a flash memory

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Flash memory controller with calibrated data communication

An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.

Multi-PAM output driver with distortion compensation

Memory controller that calibrates a transmit timing offset

A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a 'rest period' between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

Pulse control for non-volatile memory

An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

Multiphase receiver with equalization circuitry

Growing community of inventors

Los Altos, CA, United States of America

Kevin S Donnelly