International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Kevin Roy Vannorsdel

David A Freitas

Stephen A Jove

Paul Wingshing Chung

Richard Leo Galbraith

Jonathan Darrel Coker

Mantle Man-Hon Yu

Reto Josef Hermann

Walter Hirt

Wayne Leung Cheung

Francois Bernard Dolivo

Nobuya Matsubara

Calvin Shizuo Nomura

John Thomas Conteras

Masashi Murai

Steven Alan Jove

Steven Kelly Provazek

Magneto-Resistive (MR) head read/write channel () provides timer (), detector () and amplifier () to reduce the amount of time required to transition from read mode to write mode. Controller () issues the write command (WGATE) to signal a pending mode change from read to write mode. While read/write channel () remains in read mode, timer () begins a configurable countdown sequence, which allows Arm Electronics (), except for a final output stage of amplifier (), to power up in preparation for write mode. Once timer () has reached terminal count, signal (CHWGATE) is de-asserted, which causes write channel () to warm up. After warm up, write channel () writes serial data (WRITE DATA) to detector (). Still in read mode, detector () detects the presence of WRITE DATA from write channel () and asserts signal (AEWGATE). The assertion of signal (AEWGATE) cancels read mode and enables amplifier () to source current to MR head () in response to WRITE DATA to begin a fully operational write mode.

Method and apparatus for improved read-to-write transition time for a magneto-resistive head

A method and apparatus for providing quadrature biasing for coupled-pair circuits. A QBCP-circuit for quadrature amplifiers provides a new input common-mode sense point that separates the inputs for the differential-and-common mode feedback-control loops. The QBCP circuit biases all four transistors equivalently and reduces the feedback-loop interaction, thereby simplifying the bias control system and improves the voltage-transfer frequency-response performance.

Method and apparatus for providing quadrature biasing for coupled-pair circuits

A method and apparatus for providing matched differential MR biasing and pre-amplification. Tightly matched and well centered low-level MR bias voltage is provided directly to the sensing element for controlled input-impedance differential pre-amplification without common-mode voltage level control with loops.

Method and apparatus for providing matched differential MR biasing and pre-amplification

Arm electronics (AE) suitable for use in a disk drive are disclosed. The AE has write circuitry configured to operate the AE in a write mode during which a write mode supply current is drawn, and read circuitry configured to operate the AE in a read mode during which a read mode supply current is drawn. The AE uses a decaying current pulse generator that generates a decaying current pulse at the beginning of each write-to-read mode transition. The decaying current pulse has an initial value that is equal to the difference between the write mode supply current and the read mode supply current. This controlled load forces the AE to draw a gradually decreasing supply current for each write-to-read mode transition such that supply voltage transients (otherwise present due to parasitics in cabling between the AE and power supply) are reduced. Thus, the undesirable effects of such transients in the read circuitry are reduced so that write-to-read mode recovery times can be shortened.

Methods and apparatus for gradually decreasing supply current demand in arm electronics for write-to-read transitions

A method and apparatus for high voltage applications, with the latest MOSFET technology having limited terminal-to-terminal voltage capability, includes a switch circuit having at least two serially coupled MOSFETs and a two-stage MOSFET connection using a plurality of resistors, and/or a bipolar transistor, and a plurality of diodes. One of the high voltage applications is a high speed write driver in a computer disk drive. The switch circuit switches on/off between zero volt and a voltage higher than a maximum terminal-to-terminal voltage of a single MOSFET which is typically five volts. A required voltage in high voltage applications can be in excess of, for example, 8 or 9 volts.

Method and circuitry for high voltage application with MOSFET technology

This invention provide a novel class of voltage translators that translate a set of input logic levels (e.g., Low&equals;0 V and High&equals;5 V) to a set of output logic levels (e.g., Low&equals;&minus;4 V and High&equals;0 V), and vice versa, and consume no static power. In contrast to the prior art voltage translators, the output levels provided by the voltage translators of the present invention are stable and predictable, undisturbed by the state of power supply in the systems. The voltage translators of the present invention are simple in design, yet reliable and versatile in performance. They can be easily adapted to a variety of applications.

Voltage translators with zero static power and predictable performance

A method and system are disclosed for controlling the application of a reset voltage pulse to a GMR sensor in a direct-access storage device (DASD), such that existing data is not damaged or altered. Each sensor is positioned or parked at a location reserved for reset pulse application, where no valid data is stored. A complex interrelated set of commands is then initiated, and upon completion of the entire set of interrelated commands, a reset pulse is applied to the GMR sensor. Any variation or interruption in the complex interrelated set of commands will result in a disarming of the reset pulse circuitry, effectively preventing an accidental or inadvertent application of the GMR reset pulse. Alternately, a group of GMR sensors each may be tracked to a reserve track, forming a reserve cylinder. Servo marks on the reserve track are sensed by a selected sensor and utilized to ensure no valid data is present. An alternate sensor is then temporarily selected, and a reset pulse is applied, timed to avoid occurrence over a servo mark.

Method and system for GMR sensor reset pulse application

The present invention provides a method and system for translating a signal from a chip with a negative substrate bias. The method and system includes receiving an input signal in a first state in a first logic level, the first state being approximately at ground; and translating the input signal to a second state in a second logic level, the second state being above ground. The method and system translates a signal from a chip with a negative substrate bias. In the preferred embodiment, the method and system of the present invention uses a translation circuit to translate and drive the signal off-chip. The translation circuit in accordance with the present invention functions with a positive Vcc and a Vee lower than ground, and also does not violate any of the rules of functionality for components used in a chip which has a negatively biased substrate and a voltage limit on its components. The method and system allows the translated signal to be driven off-chip and be compatible with standard TTL logic levels. A pre-amp chip which uses the translation circuit of the present invention is able to maintain a fast data rate and to take advantage of the low cost of the silicon process used for the chip.

Method and system for translating TTL off-chip drive for integrated circuit with negative substrate bias

An apparatus and method for sensing and reporting connection integrity of a differential transmission line having proper parallel termination is constructed by generating an error signal which indicates that one or both differential input lines are open. The error signal is generated using a voltage comparator having a first and second input in which these inputs are coupled to the first and second ECL signal lines. The first and second input lines are also coupled to a supply voltage by a first and second dynamic impedance such that the input is pulled high when the signal lines are open. The comparator generates an error signal when the input voltages are greater than voltages normally seen on the signal lines indicating the presence of a open transmission line.

Method and apparatus to sense and report connection integrity of a

The present invention concerns an apparatus, method, and article of manufacture that satisfies the need for verifying the identity of a designated head in a gang servo head environment by querying a control parameter unit. In one embodiment, the invention may be implemented to provide a method to increase head select robustness for group head systems controlled by drive electronics. The method is practiced when a request is made for a designated head to perform a read or write operation. The request is received by a control parameter unit included in an arm electronics unit. The control parameter unit is then queried to verify the identity of the arm electronics unit selected. The identity of the designated head is then received. A parity check of the control data is performed and, assuming no errors, an actuating arm containing the designated head is positioned. The selected arm electronics unit is loaded with read or write data copied from a host system and transferred to or from the storage device. In various embodiments, the actuating arm electronics unit contain circuitry for repeatedly verifying that the proper head was selected and the integrity of data copied to the arm electronics unit.

Method and apparatus to increase head/AE select robustness for a system

A method and apparatus are provided for maximum-likelihood data detection in a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples. A plurality of digital samples are received from the ADC. The received digital samples are applied to a selected first filter and a selected second filter. The first filtered digital samples are applied to a first data detector, and the second filtered digital samples are applied to a second data detector. A predetermined parameter is identified, and at least one of the first and second data detectors is selected responsive to the identified predetermined parameter.

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San Jose, CA, United States of America

Kevin Roy Vannorsdel