Lsi Logic Corporation

Lsi Corporation

Kevin Roy Nunn

Sean Christopher Erickson

Jonathan Shaw

Eric Miller

Norman E Mause

A method for reducing the parasitic capacitance in resistors, and a resistor design embodying this method are described. By creating a p-type or an n-type implant inside of an n-well or a p-substrate, respectively, where the n-well or p-substrate is located in a p-substrate or n-substrate, respectively, a capacitively coupled capacitor is formed in series connection with the parasitic inter-layer dielectric capacitance generated when the resistor is fabricated in the dielectric material. The depletion region formed thereby behaves as a series capacitor which reduces the overall capacitance of the assemblage. The n-well or p-substrate can be placed in electrical connection with a ground potential or brought to a chosen voltage to further increase the depletion region and reduce the capacitance of the resistor.

Reduced capacitance resistors

A p-type polysilicon resistor formed in the inter-level dielectric layer contains an implanted diode. A positive voltage applied to the diode modulates the depletion region of the diode and changes the absolute resistance of the p-type polysilicon resistor. This modulation occurs not only horizontally, but also vertically. The fact that the tunable resistor is a p-type polysilicon resistor means that this structure can easily be integrated into the process since polysilicon is used as a gate material for basic CMOS processing.

High performance diode-implanted voltage-controlled poly resistors for mixed-signal and RF applications

The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains first and second contact regions extending downward from the surface of the substrate. Third and fourth contacts are also located within the diffusion region between the first and second contacts and define a conduction channel therebetween. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor; the third and fourth contacts connect to N+p&#x2212; diodes such that application of a voltage to these contacts forms respective depletion regions within the diffusion region. The depletion regions change in size depending on the voltage applied to their respective contact, thereby changing the resistance of the depletion resistor.

High performance diode implanted voltage controlled p-type diffusion resistor

A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.

Low gate resistance layout procedure for RF transistor devices

An improved semiconductor capacitor and a method for fabricating the capacitor. The capacitor is located on a substrate having a first conductive section with a first outer plate connected to a first inner plate. A second conductive section having a second outer plate connected to a second inner plate is present in the capacitor. The second inner plate is located within a first hole in the first outer plate and the first inner plate is located within a second hole in the second outer plate such that a first distance is present between the second inner plate and the first outer plate and a second distance is present between the first inner plate and the second outer plate. Multiple layers of sections like the first conductive section and the second conductive section are stacked over each other and are connected to each other as part of the capacitor. Via connections may be used to connect the layers.

Growing community of inventors

Fort Collins, CO, United States of America

Kevin Roy Nunn