International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Globalfoudries Inc.

Kevin R Winstel

Spyridon Skordas

Wei Lin

Douglas C La Tulipe, Jr

Mukta G Farooq

Kangguo Cheng

Subramanian Srikanteswara Iyer

Leathen Shi

Herbert Lei Ho

Deepika Priyadarshini

Robert Hannon

Tuan Anh Vo

Daniel C Edelstein

Fee Li Lie

Richard Paul Volant

Kamal Kumar Sikka

Dario Leonardo Goldfarb

Erdem Kaltalioglu

Paul Christian Parries

William Francis Landers

Daniel A Corliss

Troy Lawrence Graves-Abe

Dinesh Gupta

Ravi K Bonam

Iqbal Rashid Saraf

John W Golz

Maryjane Brodsky

Allan Ward Upham

Pooja R Batra

Da Song

Anthony K Stamper

Bing Dang

Joshua T Smith

Kevin Shawn Petrarca

Edmund Juris Sprogis

John Anthony Fitzsimmons

Emily R Kinser

Cornelius Brown Peethala

Cornelia K Tsang

Ravi Mahendra Todi

Sarah Huffsmith Knickerbocker

Richard Francis Indyk

Xi Li

Gerd Pfeiffer

Scott R Stiffler

Brown Cornelius Peethala

Yoichi Otani

Teresa Jacqueline Wu

Scott D Allen

Alex Richard Hubbard

Jonathan E Faltermeier

Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.

Microfluidic chips with one or more vias

The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Three-dimensional microelectronic package with embedded cooling channels

An apparatus that includes a solution bath of a seasoned solution, the seasoned solution containing a mixture of hydrofluoric acid, nitric acid, and acetic acid; and one or more silicon wafers being suspended in a position above the solution bath, wherein at least a portion of the mixture having been used in thinning the one or more silicon wafers.

Selective etching of silicon wafer

A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.

Semiconductor device including built-in crack-arresting film structure

Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.

Edge trim processes and resultant structures

A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.

Substrate bonding with diffusion barrier structures

Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.

Strain detection structures for bonded wafers and chips

The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.

Combination of TSV and back side wiring in 3D integration

According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.

The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.

Handler wafer removal by use of sacrificial inert layer

A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1&#xd7;10atoms/cm; collecting the mixture after reacting with the boron doped portions of the one or more silicon wafers; and adding collected mixture back into the solution container to create the etch solution.

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Poughkeepsie, NY, United States of America

Kevin R Winstel