Apple Inc.

Here Global B.v.

Kevin R Walker

John H Mylius

Deniz Balkan

Manu Gulati

James D Ramsay

Mitchell Palmer Lichtenberg, Jr

Matthew John Byom

Russell Alexader Blaine

John-Rhys Newman

Duncan Burns

Shantonu Sen

Pascal Wever

Julian Bleecker

Daniel Heller

Charlie Sutton

Sebastian Frey

Brody Larson

Jeremy Matters

Simon James

Vidyut Samanta

David Vegezzi

Pawena Thimaporn

Tom Arbisi

Markus Eklund

Mitchell P Lichtenberg

Dae-Han Yi

Audrey Lee

Display screen or portion thereof with virtual character

A method, apparatus and computer program product are provided to facilitate the display of data in conjunction with an image. In the context of a method, an image is caused to be presented and input is received via a rotatable dial wheel while the image is presented. The method also includes determining data to be presented based upon the input. In this regard, the method modifies the data to be presented in response so the rotation of the dial wheel. Further, the method causes the data that is determined based on the input to be presented concurrent with the image.

Method and apparatus for controlling data overlaid upon an image

A system and method for efficiently monitoring traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes multiple bus event filters. Programmable configuration registers are used to assign the bus event filters to selected buses for monitoring associated bus traffic and determining whether qualified bus events occur. If so, the bus event filters increment an associated count for each of the qualified bus events. The values used for determining qualified bus events may be set by programmable configuration registers.

Programmable resources to track multiple buses

Methods, machine-readable tangible storage media, and data processing systems that enable a debug host device to acquire memory dump information from a debug target device after the target device suffers an unrecoverable system malfunction are disclosed. In one embodiment, data in the volatile memory on a debug target device is accessed via a hardware integrated debug framework, which is also used to access data on a nonvolatile electronically erasable semiconductor memory of a debug target device, and one or more registers of one or more processors on a debug target device, and a core dump is created on the debug host device.

Enhanced debugging for embedded devices

A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes a trace buffer with multiple physical partitions assigned to subsets of the multiple buses. The number of partitions is less than the number of multiple buses. One or more trace instructions may cause a trace history, trace bus event statistics, local time stamps and a global time-base value to be stored in a physical partition within the trace buffer.

Efficient trace capture buffer management

A debug port configured to generate and provide a return clock is disclosed. In one embodiment, an integrated circuit (IC) includes one or more functional units and a debug port (DP). The DP is configured to enable access by an external debugger to the functional unit(s) of the IC for debugging purposes. The DP includes circuitry that may generate a first clock signal that is provided to the functional unit(s) during debug operations. Receiving test result data at the DP may require a return clock signal that is not provided by the functional unit(s). Accordingly, the IC may include a clock modifier coupled to receive the first clock signal. The clock modifier may generate a second clock signal based on the first, the second clock signal being provided to the DP as a return clock signal.

Debug access with programmable return clock

A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Debug registers for halting processor cores after reset or power off

In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Program counter (PC) trace

Growing community of inventors

Los Gatos, CA, United States of America

Kevin R Walker