Micron Technology Incorporated

Kevin R Duncan

Joseph P Kerzman

Steven G Wurzer

Neil Petrie

Terry M Cronin

Prateek Sharma

Bridget L Mallak

An example apparatus can include a memory device and a controller coupled to the memory device configured to receive a command including command information to access a register from a host device. The controller can grant access to the register in response to the controller determining the command is valid and/or deny access to the register in response to the controller determining the command is invalid. The controller can determine the command is valid by calculating an answer using a seed from the command in a formula and verifying the calculated answer matches an answer from the command. The command, once verified as valid, can allow the host device to access configuration registers and/or data registers.

Register access

A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.

Function arbitration and quality of service for memory commands

An example apparatus can include a host device and an apparatus including a memory device and a controller coupled to the memory device, wherein the host device is configured to send a command to read an image to configure the host to boot from the memory device to the controller and wherein a base address register is configured to receive the command, indicate the size of the image, and redirect the command to a first image in memory using a first register that indicates a size of the first image and a second register that indicates a location of the first image.

Configurable option ROM

A peripheral component interconnect express (PCIe) physical function is coupled to a controller. The controller is configured to allocate a first portion of resources for use by the PCIe physical function. A PCIe virtual function is coupled to the controller. The is configured to allocate a second portion of resources for use by the PCIe virtual function based, at least in part, on a total number of PCIe physical functions and a total number of PCIe virtual functions associated with the apparatus.

Dynamic allocation of resources of a storage system utilizing single root input/output virtualization

A command to duplicate data on a storage system is received from a host system, and in response to receiving the command, data corresponding to the command is retrieved from host memory of the host system. A plurality of write operations are performed on one or more memory devices of the storage system to fulfill the command, wherein performing each one of the plurality of write operations comprises writing the data to the one or more memory devices of the storage system without a subsequent retrieval of the data from the host memory.

Writing same data on a storage system

A command from a host is received via a port of a storage system. The port is assigned a current port revision identifier. The current port revision identifier of the port is associated with the command. Responsive to a status change associated with the port, an updated port revision identifier is assigned to the port to replace the current port revision identifier of the port and execution of the command is aborted responsive to determining that the current port revision identifier associated with the command is different than the updated port revision identifier of the port.

Command processing for a storage system

Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

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Ramsey, MN, United States of America

Kevin R Duncan