International Business Machines Corporation

Kevin Paul Demsky

Matthew James Paschal

Ladd William Freitag

Steven John Baumgartner

John Farley Ewen

Randolph B Heineke

Raymond J Thatcher

Daniel Scott Hedin

London Terry Brown

A test method and apparatus are provided for testing parallel optical transceivers. Each of a plurality of channels of the parallel optical transceiver is connected in series. A predefined data pattern is applied to a first channel of the series connected plurality of channels. An output is detected from a last channel of the series connected plurality of channels and compared the applied predefined data pattern to identify operation of the parallel optical transceiver. An optical wrap plug and an electrical wrap plug are used for connecting in series the plurality of channels of the parallel optical transceiver. The optical wrap plug includes a plurality of optical connectors for respectively optically connecting each respective channel transmitter to a next respective channel receiver. The electrical wrap plug includes a plurality of electrical connectors for respectively electrically connecting a respective channel receiver to a corresponding respective channel transmitter.

Test method and apparatus for parallel optical transceivers using serial equipment

An on-chip parallel data generator, including a Built In Self Test (BIST) generator, is integrated into a laser driver array of a parallel optical communication transmitter so that all optical outputs switch simultaneously. The BIST generator requires only one clock input which clocks the BIST generator for all channels. The optical outputs respond to either the on-chip BIST generator or the electrical inputs if a valid signal is present on the inputs.

Built in self test method and circuit for parallel optical transmitters

A method and apparatus are provided to ensure that laser optical power does not exceed a &ldquo;safe&rdquo; level in a DC coupled open loop parallel optical link in the event that a fiber optic ribbon cable is broken or otherwise severed. A duplex parallel optical link includes a transmitter and receiver pair and a fiber optic ribbon that includes a designated number N of channels that cannot be split. The duplex transceiver includes a corresponding transmitter and receiver that are physically attached to each other and cannot be detached therefrom, so as to ensure safe, laser optical power in the event that the fiber optic ribbon cable is broken or severed. Safe optical power is ensured by redundant current and voltage safety checks, and the corresponding low duty cycle signal is generated by a safety pulse generator in the safety channel.

Laser safety method for DC coupled parallel optical link

Optical power adjustment is provided for parallel optical transmitters, in particular, for an array of vertical cavity surface emitting lasers (VCSEL's). The lasers in the array can be independently digitally adjusted with associated digital circuitry to compensate for manufacturing and temperature variations. In particular, the threshold current and modulation current for each VCSEL in the array, as well as a global temperature coefficient for all the VCSEL's in the array, can be digitally setup and adjusted for desired power levels. Once set, the associated digital code can be stored in non-volatile memory, and loaded at powering-up of the transmitters.

Optical power adjustment circuits for parallel optical transmitters

A ring oscillator, such as a bipolar ring oscillator with enhanced, fast startup and shutdown includes a series of a plurality of inverting differential stages connected in a loop. The plurality of inverting differential stages includes a first multiplexer stage. The first multiplexer stage includes a first signal input, a second signal input and a select input. An oscillator feedback signal is applied to the first signal input of the first multiplexer stage. A startup circuit is coupled to the first multiplexer stage. The startup circuit includes a differential signal coupled to the second signal input of the first multiplexer stage for starting the bipolar ring oscillator. The startup circuit applies a full differential switching voltage signal to the second signal input of the first multiplexer stage to guarantee start of the bipolar ring oscillator after one delay of the series of the plurality of inverting differential stages connected in the loop. The startup circuit includes a fast transition run signal and a multiplexer select signal responsive to the run signal. The multiplexer select signal is coupled to the select input of the first multiplexer stage for controlling the first multiplexer stage to select the oscillator feedback signal or the static differential signal for stopping the bipolar ring oscillator.

Bipolar ring oscillator with enhanced startup and shutdown

A selectable receiver includes a first receiver module for receiving first input signal type and a second receiver module, different from the first receiver module, for receiving a second input signal type, both receiver modules coupled to the same receiver inputs. An internal common mode voltage for the first signal type or for the second signal type, is provided by respective common mode voltage networks, to the first or to the second receiver module, to facilitate AC coupling with the appropriate DC common mode voltage required by the signal type. If direct coupled, the internal common mode voltage is effectively swamped out by the common mode voltage of the input signal. The first receiver module or the second receiver module, and the associated first common mode voltage or second common mode voltage, are selected in the receiver based on a control signal. The first receiver module can be a current mode logic (CML) receiver, and the second receiver module can be a low-voltage differential (LVDS) receiver module, e.g., a self-timed interface (STI) receiver module.

Selectable low-voltage differential signal/current mode logic (LVDS/CML) receiver with the option of AC or DC coupling

The constant current source circuit provides current that compensates for changes in performance resulting from changes of temperature. The circuit mixes variable amounts of current having a negative temperature coefficient with current having a positive temperature coefficient. Analog and digital embodiments of the circuit are disclosed. In the analog embodiment, the amount of current having a positive temperature coefficient is added to an amount of current having a negative temperature coefficient as determined by the voltage difference between a variable control voltage input to transistors and a bandgap reference voltage. A transistor in each of two current selectors is connected to the variable control voltage, one of which is connected to ground and the other of which is output; and another transistor in each current selector is connected to the reference voltage, and again one transistor is grounded and the other is output whose current is mixed with the output from the transistor in the first current selector connected to the variable control voltage. A continuous range of temperature coefficients are realizable by varying the control voltage with respect to the bandgap reference voltage. The digital embodiment has a digital-to-analog converter connected to a bias voltage from the current having a positive temperature coefficient and a second digital-to-analog converter connected to a second bias voltage from the current having a negative temperature coefficient. A digital input signal to a corresponding switch determines if its respective transistor in each of the digital-to-analog converters conduct current. The two digital-to-analog converters may be configured in a common centroid arrangement of integrated complementary unit cells. The constant current source circuit can be used to drive off-chip parallel loads such as VCSELs.

Constant current source circuit with variable temperature compensation

A redundant resistor matching detector is provided with constant percentage threshold. The redundant resistor matching detector includes a voltage reference and a first operational amplifier, a second operational amplifier, a first potentiometer and a reference potentiometer. The first operational amplifier has a first input connected to a first potentiometer. The second operational amplifier has a first input connected to the reference potentiometer. The first operational amplifier and the second operational amplifier have a reference input coupled to the voltage reference. An input current mirror is coupled to the first potentiometer providing a first current. A first reference current mirror is coupled to the reference potentiometer providing a reference current. A second reference current mirror has an input coupled to a first output of the first reference current mirror and has a first output coupled to an output of the input current mirror. A pair of series connected resistors are connected between a second output of both the first reference current mirror and the second reference current mirror. A resistor is connected between a junction of the pair of series connected resistors and the first outputs of the input current mirror and the second reference current mirror.

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Rochester, MN, United States of America

Kevin Paul Demsky