Texas Instruments Corporation

Kevin Patrick Lavery

Karl Friedrich Greb

Sunil Suresh Oak

Alexandre Pierre Palus

Yanyang Xiao

Paul William Krause

Jim Childers

Pravin P Patel

Steven Grey Howard

Jason P Whiles

A measurement system includes a current source that is arranged to generate a current pulse to charge a capacitor as a function of an input clock signal. The accumulated charge on the capacitor is converted to a sample (e.g., resultant digital value) by an ADC (analog-to-digital converter). The samples can be aggregated as a distribution in order to estimate the jitter of the input clock signal. Variability of the measurement system can be minimized through calibrating the device-under-test at specific points of PVT (process, voltage, and temperature) conditions. A confidence metric such as a standard of deviation can be derived from the associated samples. The measurement system can be included on a substrate that includes the oscillator that generates the input clock signal.

Controlling clock measurement with transistors, capacitor, OPAMP, ADC, external enable

An electronic circuit includes a microcontroller processor (), a peripheral () coupled with the processor, an endian circuit () coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit () to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Endian configuration memory and ECC protecting processor endianess mode circuit

Encode and multiplex, register, and decode and error correction circuitry

A time-out period is established for a watchdog timer. The time-out period is restarted each time a designated key value is received when each key value is received in a proper sequence. An error is indicated if set of key values is received in an incorrect sequence. A time-out is indicated if a correct sequence of key values is not received within the time-out period.

Watch dog timer and counter with multiple timeout periods

A soft-error resistant redundant latch including a first stage and second stage, each stage coupled to receive and to latch a binary signal in a latched state. Each stage is arranged to maintain the latched state at an intermediary node of the stage in response to a feedback path internal to the stage and in response to a stage output signal from the other stage. Each stage is arranged to generate a stage output signal in response to the latched state of the stage. The state of each stage is set to a first selected state by selectively coupling a stage set transistor between a first power rail and the intermediary node of the first stage in response to a set signal. The stage set transistor of the first stage and the stage set transistor of the second stage are complementary types.

Soft-error resistant latch

Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance.

Method and system to reduce electromagnetic radiation from semiconductor devices

In response to a selected analog applied to the input terminal of an analog-to-digital converter, the digitized output signal is stored in a buffer/register. In making a comparison with a predetermined value, a second buffer/register stores either a preselected value or a second digitized signal. A comparator is coupled to the first and the second buffer/register to provide the result of a comparison. In this manner, the central processing unit is not involved in the comparison testing procedure.

Growing community of inventors

Sugar Land, TX, United States of America

Kevin Patrick Lavery