Arm Limited

Kevin P Welton

Stuart David Biles

Paul Gilbert Meyer

Nigel C Paver

A data processing system including a plurality of processorseach having a local cache memoryis provided. A cache coherency controllerserves to maintain cache coherency between the local cache memories. When one of the processorsis placed into a low power state its associated local cache memoryis maintained in a state in which the data it is holding is accessible to the cache coherency controlleruntil a predetermined condition has been met whereupon the local cache memoryconcerned is placed into a low power state. The predetermined condition can take a variety of different forms such as the rate of snoop hits falling below a threshold value, the ratio of snooping hits to snoop requests falling below a threshold value, a predetermined number of clock cycles passing since the associated processor for that local cache memory was powered down as well as other possibilities.

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Austin, TX, United States of America

Kevin P Welton