Texas Instruments Corporation

Kevin P Lyne

Kurt Peter Wachtler

Peter R Harper

Kenneth Robert Rhyner

David G Wontor

A method for fabricating a semiconductor device provides a first chip having first terminals, a second chip having second terminals, and a third chip having third terminals. A first silicon interposer having first through silicon vias TSVs and a second silicon interposer having second TSVs is provided. The first TSVs are arrayed in a first, a second, and a third set. The first set is located in a first interposer region and matching the first terminals. The second set is located in a second interposer region and matching the second terminals. The third set is located in a third interposer region between the first and second regions and matching the TSVs of the second interposer and the third terminals. The first chip is aligned with the first set TSVs. The second chip is aligned with the second set TSVs. The second interposer is aligned with the third set TSVs. A solder of a first melting temperature is used.

Heterogeneous integration of memory and split-architecture processor

A standard memory chip () is vertically assembled with two processor chips () of split architecture by means of a small silicon interposer () stacked onto a large silicon interposer (); both interposers include through-silicon vias (TSVs), while the chips are free of TSVs. The TSVs of small interposer () connect to the memory chip () and to the bottom interposer (). Symmetrically positioned relative to interposer (), and connected to it by short signal traces, chips () are attached to the TSVs of interposer, which in turn is attached to a substrate () with supply connections.

3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor

A semiconductor flip-chip ball grid array package () with one-metal-layered substrate. The sites () of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (), when the sites can be routed for metal plating (). The space to place a maximum number () of signal routing traces is opened up by interrupting the periodicity of the site array from the edge () of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.

BGA package with traces for plating pads under the chip

The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

Device and method for including passive components in a chip scale package

A modeling technique for selectively depopulating solder balls ( ) (and their respective solder ball pads ( ), vias ( ) and traces or lines ( )) from a conventional foot print of a ball grid array (BGA) package, or land grid array package (LGA) to improve device reliability. The modeling technique anticipates a routing of traces through the gap resulting from the depopulated solder balls or lands as additional space for routing traces or lines from solder ball or land pads to an exterior surface of a substrate ( ) upon which a semiconductor die ( ) is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls or lands on ever shrinking packages, thereby increasing device reliability.

Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability

A routing technique for improving device reliability by selectively depopulating solder balls (,) (and their respective solder ball pads (,), vias (,) and traces or lines (,)) from a conventional foot print of a ball grid array (BGA) package, and a BGA package so modified. The routing technique uses the gap resulting from the depopulated solder balls as additional space for routing traces or lines from solder ball pads to an exterior surface of a substrate (,) upon which a semiconductor die (,) is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls on ever shrinking packages, thereby increasing device reliability.

Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified

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Plano, TX, United States of America

Kevin P Lyne