Intel Corporation

Kevin O'Brien

Kaan Oguz

Brian S Doyle

Mark L Doczy

Christopher J Wiegand

Charles C Kuo

Tanay Gosavi

Noriyuki Sato

Tahir Ghani

Oleg Golonzka

Md Tofizur Rahman

Sasikanth Manipatruni

Justin Brockman

Ian A Young

Angeline Smith

Tofizur Rahman

Satyarth Suri

Benjamin Buford

Michael D Goodner

Robert P Meagley

Robert S Chau

Chia-Ching Lin

Brian Maertz

Patrick R Morrow

Uygar E Avci

Ashish Verma Penumatcha

Carl H Naylor

Chelsey Dorow

Kirby Maxey

Gary Allen

Grant M Kloster

Shriram Shivaraman

Daniel Ouellette

Sudarat Lee

Prashant Majhi

Mauro J Kobrinsky

Elijah V Karpov

Hui Jae Yoo

Christopher J Jezewski

David L Kencke

Shriram Ramanathan

Steven W Johnston

Abhishek A Sharma

Justin K Brask

Kevin Lai Lin

Sarah E Kim

David H Gracias

Tejaswi K Indukuri

Tian-An Chen

James M Powers

Thomas N Marieb

Juan G Alzate Vinasco

Michael Y Chan

Michael C Harmes

Scott List

Adrien Lavoie

Rishabh Mehandru

Valluri Ramana Rao

Valery M Dubin

Paul B Fischer

Kimin Jun

Bruce A Block

Chris E Barns

Peter K Moon

Juan E Dominguez

Nafees Kabir

Doug B Ingerly

Anne E Miller

Sridhar Balakrishnan

Heidi B Cao

James Pellegren

Donald Bruner

Ravi Pillarisetty

Matthew V Metz

Adel A Elsherbini

Niloy Mukherjee

Dmitri E Nikonov

Seung Hoon Sung

Uday Shah

Henning Braunisch

Manish Chandhok

Robert L Bristol

Yih Wang

Rami Hourani

Szuya S Liao

Krishna Bharath

Eungnak Han

Ramanan Chebiam

Harsono S Simka

Makarem A Hussein

Jun He

David Walter Peters

Hyun-Mog Park

Gurpreet Singh

Vijayakumar S Ramachandrarao

Ying Zhou

Daniel B Bergstrom

Chin-Chang Cheng

David Michael Thompson

Sarah Atanasov

A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.

Encapsulation for transition metal dichalcogenide nanosheet transistor and methods of fabrication

Transistors, devices, systems, and methods are discussed related to transistors including a number of 2D material channel layers and source and drain control electrodes coupled to source and drain control regions of the 2D material channels. The source and drain control electrodes are on opposite sides of a gate electrode, which controls a channel region of the 2D material channels. The source and drain control electrodes provide for reduced contact resistance of the transistor, the ability to create complex logic gates, and other advantages.

Contact gating for 2D field effect transistors

Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

Transistors with monocrystalline metal chalcogenide channel materials

A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

Transition metal dichalcogenide nanosheet transistors and methods of fabrication

A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

Transition metal dichalcogenide nanowires and methods of fabrication

A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

Transition metal dichalcogenide (TMD) layer stack for transistor applications and methods of fabrication

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Integrated circuit device structures and double-sided electrical testing

A memory apparatus includes a first electrode having a spin orbit material. The memory apparatus further includes a first memory device on a portion of the first electrode and a first dielectric adjacent to a sidewall of the first memory device. The memory apparatus further includes a second memory device on a portion of the first electrode and a second dielectric adjacent to a sidewall of the second memory device. A second electrode is on and in contact with a portion of the first electrode, where the second electrode is between the first memory device and the second memory device. The second electrode has a lower electrical resistance than an electrical resistance of the first electrode. The memory apparatus further includes a first interconnect structure and a second interconnect, each coupled with the first electrode.

Spin orbit memory devices with dual electrodes, and methods of fabrication

Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

Ferroelectric field effect transistors (FeFETs) having band-engineered interface layer

A multilayer conductive line is disclosed. The multilayer conductive line includes a dielectric layer, a Ta barrier layer on the dielectric layer and a superlattice on the Ta barrier layer. The superlattice includes a plurality of interleaved ferromagnetic and non-ferromagnetic material.

Method to fabricate metal and ferromagnetic metal multilayer interconnect line for skin effect suppression

A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

Two terminal spin orbit memory devices and methods of fabrication

An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

Spin orbit torque device with insertion layer between spin orbit torque electrode and free layer for improved performance

An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.

Perpendicular exchange bias with antiferromagnet for spin orbit coupling based memory

A pSTTM device includes a first electrode and a second electrode, a free magnet between the first electrode and the second electrode, a fixed magnet between the first electrode and the second electrode, a tunnel barrier between the free magnet and the fixed magnet, a coupling layer between the free magnet and the first electrode, where the coupling layer comprises a metal and oxygen and a follower between the coupling layer and the first electrode, wherein the follower comprises a magnetic skyrmion. The skyrmion follower may be either magnetically and electrically coupled to the free magnet to form a coupled system of switching magnetic layers. In an embodiment, the skyrmion follower has a weaker magnetic anisotropy than an anisotropy of the free magnet.

Perpendicular spin transfer torque memory (pSTTM) devices with enhanced thermal stability and methods to form the same

A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

Spin orbit torque (SOT) memory devices and methods of fabrication

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Portland, OR, United States of America

Kevin O'Brien