International Business Machines Corporation

Globalfoundries Inc.

Kevin N Ogg

Jeffrey P Gambino

Richard John Rassel

Richard L Rassel

Robert K Leidy

Zhong-Xiang He

Robert Mark Rassel

Daniel Nelson Maynard

Timothy G Dunham

Jeanne-Tania Sucharitaves

Raymond J Rosner

Valarmathi C Shanmugam

Anthony K Stamper

James William Adkisson

Mark David Jaffe

Jason D Hibbeler

Bradley Alan Orner

Panglijen Candra

Robert L Barry

Phillip Francis Chapman

Michael Lawrence Gautsch

A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.

Metal insulator metal (MIM) capacitor structure

Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.

Segmented guard ring structures with electrically insulated gap structures and design structures thereof

A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.

Intralevel conductive light shield

A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.

Image sensor pixel structure employing a shared floating diffusion

A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.

Interlevel conductive light shield

Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.

IC chip and design structure including stitched circuitry region boundary identification

Stitched circuitry region boundary identification for stitched IC chip layout

A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.

Optical sensor including stacked photodiodes

Optical sensor including stacked photosensitive diodes

Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip layout exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.

Stitched IC chip layout design structure

Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout includes for at least one stitched region of a plurality of stitched regions: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithographic tool field at the second entity.

Growing community of inventors

Burlington, VT, United States of America

Kevin N Ogg