Matsushita Electric Industrial Co., Ltd.

Kevin Mark Stone

Hidetoshi Suzuki

Minoru Okamoto

Hideyuki Kabuo

Ryutaro Yamanaka

A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.

Communications digital signal processor and digital signal processing method

A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register&#x2014;register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.

Processing unit and processing method

A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.

A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM and PM of an old state is added to each branch metric BM and BM separately. A path metric of a new state N is formed by comparing the value of PM &plus;BM to the value of PM &plus;BM . A path metric of a new state N&plus;2 is formed by comparing the value of PM &plus;BM to PM &plus;BM

Two path metrics (PM,, PM,) are read from path metric storing means,, and two path metrics (BM,, BM,) are read from branch metric storing means,. An ACS operation is executed using PM,&plus;MB,and PM,&plus;BM,by comparing means,, adding means,, comparison result storing means,, and selecting means,. In parallel with the ACS operation, an ACS operation is executed using PM,&plus;MB,and PM,&plus;BM,by comparing means,, adding means,, comparison result storing means,, and selecting means

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Kevin Mark Stone