Texas Instruments Corporation

Power Signal Technologies, Inc.

Kevin M Ovens

Jeffrey A Niehaus

Clive D Bittlestone

Patrick Robert Smith

Bobby D Strong

Jay A Maxey, Jr

Robert C Martin

Craig B Greenberg

Steven A Hunley

Bob Helmick

Shivaling S Mahant-Shetti

James Fred Salzman

Robert J Landers

Henry M Darley

Roland H Pang

Alan Stephen Bass

Bob D Strong

Carl J Scharrer

Robert A Helmick

Byron Mitchell Reed

Tom Shinham

Dale C Earl

W T Greer, Jr

Mike Hutchison

David S Shaffer

Jay Maxey

John D Marsh

Thomas C Shinham

Systems and methods are disclosed to mitigate power consumption in a power supply, such as when operating in a low power mode. One aspect of the present invention relates to a control system for a power supply. The system includes a bias generator that provides a bias signal operative to charge a storage device based on a control signal. During a low power mode, a control system provides the control signal with a predetermined duty cycle that is functionally related to a storage capacity of the storage device.

Low power control mode for power supply

A solid state light apparatus ideally suited for use in traffic control signals provided with optical feedback to achieve a constant light output, preferably by detecting back-scattered light from a diffuser centered above an LED array. The control logic allows for the LEDs to be individually driven, and having their drive characteristics changed over time to ensure a uniform beam of light is generated at an intensity meeting DOT standards, across the life of the device. The optical feedback also establishes the uniform beam intensity level as a function of sensed ambient light to discern day and night operation.

Solid state light with controlled light output

A stacked logic circuit ( ) having a serially connected first logic circuit ( ) operating off a first voltage differential and providing in series with a second logic circuit ( ) operating off a second voltage differential. The second logic circuit being in series with the first logic circuit recycles the current of the first logic circuit. A low impedance shunt circuit ( ) is provided in parallel with the first logic circuit ( ) and shunts additional current required of and to the second logic circuit ( ) from the single voltage source (V ). A Zener diode (Z ) shunts current from the first logic circuit not required by the second logic circuit via a shunt node (N). The shunt circuit ( ) includes a Darlington pair of transistors or a three terminal voltage regulator ( ) and only shunts a very small amount of current to ground. The stacked logic circuit of the present invention efficiently uses current drawn by the single voltage source to reduce power consumption.

Control circuit having stacked IC logic

A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.

Automated well-tie and substrate contact insertion methodology

An integrated circuit (IC) comprising an integrated level shifting latch for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.

Circuit and method for an integrated level shifting latch

A phase/frequency detector (18) includes a first memory circuit (50), a second memory circuit (52), a first set circuit (54), a second set circuit (58) and a reset circuit (56). The first memory circuit (50) provides a first output signal (20) in response to the first input signal (12). The second memory circuit (52) provides a second output signal (22) in response to the second input signal (14). The first set circuit (54) initiates the transition of the first memory circuit (50) to the active state, and the second set circuit (58) initiates the transition of the second memory circuit (52) to the active state. The reset circuit (56) initiates the transition of the memory circuits (50, 52) to the inactive state.

High speed phase/frequency detector

An integrated circuit (100) contains an analog phase-locked loop circuit having a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector circuit for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG). The voltage controlled oscillator circuit is designed to work with a relatively low regulated voltage, and the regulator circuit is implemented with n-channel devices. The two control voltages respectively effect coarse and fine adjustment of the frequency of the output signal from the phase-locked loop circuit.

Method and apparatus for effecting analog phase-locked loop control of a

An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The integrated circuit (100) has a plurality of external connection pins (104, 106), which are coupled to the other circuitry. The analog phase-locked loop circuit (10) is free of connections to the external connection pins. The analog phase-locked loop circuit (10) includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG) and a regulated supply voltage (VREG).

Analog phase-locked loop including voltage regulator

An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The analog phase-locked loop circuit includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG), one of which also serves as a regulated supply voltage. The regulator circuit includes n-channel devices which are connected in series between a supply voltage and each control voltage output.

Voltage regulator circuit and phase-locked loop using same

A lock detector (16) includes a set circuit (64), a reset circuit (120), and a latch circuit (80). The latch circuit (80) provides an output signal (82) in response to the temporal relationship of the first input signal (12) and the second input signal (14). The set circuit (64) initiates the transition of the latch circuit (80) to the locked state, while the reset circuit (120) initiates the transition of the latch circuit (80) to the not-locked state.

High speed lock detector

A digital data signal voltage converter for converting a first digital data signal that is asserted at a first pair of voltage levels that are considered the inverse of one another, the two voltage levels being a first low voltage level and a first high voltage level, to a second digital data signal that is asserted at a second pair of voltage levels that are considered the inverse of one another, the second pair of voltage levels being a second low voltage level and a second high voltage level, the second high voltage level being higher than the first high voltage level. The voltage converter includes an active pull-up transistor and an active pull-down transistor, along with circuitry for controlling the second high voltage level. Three-state control may be provided to allow use as an input/output terminal.

Voltage converting I/O driver circuit

An integrated circuit (42) is formed in a semiconductor layer (50) having a defined area. Functional circuitry (12) is formed in semiconductor layer (50) to occupy only a portion of the defined area of semiconductor layer (50), and thus defining an unoccupied area of semiconductor layer (50). A capacitor is formed in semiconductor layer in a substantial portion of the unoccupied area.

Integrated circuit

A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal. ON the positive going edge of the clock signal, data is transferred from the storage node (66) to the slave storage node (80) and then latched in the latch (82) on the negative going edge of the clock signal. This results in a minimum number of inverters, thus decreasing the Clock-to-Q time.

High speed flip-flop for gate array

A process variance detection technique for detecting fabrication processing variances in integrated circuit components, such as resistors or MOSFETs, is based on the decreased sensitivity to processing variations exhibited by components that are up-sized relative to similar components with nominal dimensions. Detection circuitry includes detection components with both nominal and up-sized dimensions, and variance detection involves detecting the differences in operational response of the nominal and up-sized detection components. For bipolar logic, resistors are fabricated with up-sized widths, while for MOS logic, MOSFETs are fabricated with up-sized gate lengths.

On-chip variance detection for integrated circuit devices

A flip-flop having a master section including two switching transistors is provided with output loading transistors to drive the two transistors into saturation in the event of a metastable condition causing input is present. By driving the switching transistors into saturation they become inactive and background noise cannot cause proprogation of the metastable condition to subsequent flip-flip stages.

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Garland, TX, United States of America

Kevin M Ovens