International Business Machines Corporation

Kevin M Mcilvain

Kyu-hyoun Kim

Warren Edward Maule

Saravanan Sethuraman

Adam J McPadden

Stephen P Glancy

Lucas W Mulkey

Briana E Foxworth

Edgar Rolando Cordero

Gary A Van Huben

Nandita A Mitra

Robert Brett Tremaine

Anuwat Saetow

David D Cadigan

Kyu-Hyoun Kim

Frank LaPietra

Krishna Thangaraj

Jeremy R Neaton

Richard D Wheeler

Ryan Patrick King

Feihong Yan

Andre A Marin

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Efficient and selective sparing of bits in memory systems

A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel

Aspects include configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test. Test traffic is arbitrated between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device. One or more protocol specific conversions are performed between the test traffic and a device-specific packeted protocol of each of the devices under test. Payload checking is performed between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases.

Packeted protocol device test system

Disclosed is a computer implemented method to mark data as persistent using spare bits. The method includes receiving, by a memory system, a set of data, wherein the set of data includes a subset of meta-bits, and the set of data is received as a plurality of transfers, and wherein the memory system includes a first rank and a second rank. The method also includes decoding, by a decoder, the subset of meta-bits, wherein the subset of meta-bits are configured to indicate the set of data is important. The method further includes storing, based on the decoding, the set of data in a persistent storage medium.

Using spare bits in memory systems

A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.

Using dual channel memory as single channel memory with spares

Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Thermal and power memory actions

A technique relates to operating a memory controller. A feedback mode is initiated such that an identified memory device of first memory devices includes an identified bit lane on a data bus to be utilized for testing. A process includes sending commands on the-N bit lanes of the command address bus to a buffer and duplicating commands designated for a selected one of the-N bit lanes. The process includes sending the duplicated commands on the identified bit lane in route to the buffer, and receiving a result of a parity check for the commands sent on the-N bit lanes, such that when the result is a pass the process ends. When the result is a fail, a duplicated parity check is performed using duplicated commands on the identified bit lane in place of the selected one. When the duplicated parity check passes, the selected one is bad.

Using dual channel memory as single channel memory with command address recovery

An NVDIMM requests an authentication object in response to a detected command to initiate a save operation to copy first memory data located in volatile memory on the NVDIMM to non-volatile memory located on the NVDIMM. The NVDIMM determines based on the authentication object that authentication has failed. The NVDIMM implements, in response to determining that authentication has failed, a security measure to prevent recovery of the first memory data.

Memory security protocol

A three-dimensional stacked (3DS) memory module includes multiple memory chips physically integrated with a data I/O chip. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through all available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to de-activate one or more of the data interfaces (for example, to reduce power consumption). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.

Power management in multi-channel 3D stacked DRAM

A nonvolatile queue manager queues entries of host data from one or more host channels to one or more write buffers for storage in one or more nonvolatile memory devices of a nonvolatile memory array. The nonvolatile queue manager compares a number of the entries queued to one or more nonvolatile memory holdup power write thresholds based on detecting a power loss event. The nonvolatile queue manager tracks one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds. The nonvolatile queue manager initiates a mitigation action on a subsequent restoration of power to handle the one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds.

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Delmar, NY, United States of America

Kevin M Mcilvain