Hewlett-packard Development Company, L.P.

Kevin M Laake

Barry Joseph Arnold

Navin Amar Ghisiawan

Andrew R Allen

John Richard Howlett

One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or more lines terminated by the termination circuitry, shunting current from the termination voltage supply and through the termination voltage delivery network in response to a second signal on one or more terminated lines, and helping to reduce the shunted current for extended shunting.

Shunted current reduction

A method of modifying data of functional latches of a logic unit during scan chain testing thereof to verify a test case failure of a suspected cell comprises: (a) determining a test case failure in the logic unit through scan chain testing thereof; (b) suspending clocked operations of the logic unit; (c) during suspended clocked operations of the logic unit, performing the following steps: (i) reading logic states of the functional latches; and (ii) modifying the logic state of at least one of the functional latches based on the determined test case failure; (d) restarting clocked operations of the logic unit; and (e) reading logic states of the functional latches resulting from the modification to verify the test case failure of a suspected cell.

Method and system of modifying data in functional latches of a logic unit during scan chain testing thereof

An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit pattern generator in one of the I/O driver/receivers drives a bit pattern through a driver to the connected pads. The bit pattern is then driven through the receiver of a second I/O driver/receiver to a first clocked register. An identical bit pattern generator in the second I/O driver/receiver then drives an identical bit pattern into a second clocked register. A comparator compares the outputs of these two registers. If the two bit patterns don't match, the comparator signals there is a functional problem with one of the I/O driver/receivers.

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Fort Collins, CO, United States of America

Kevin M Laake