Hewlett-packard Company

Agilent Technologies, Inc.

Kevin M Hall

Rodney H Orgill

Charles L Cruse, Jr

Bob J Self

Bobby Joe Self

Daniel A Schmelzer

A system includes an interconnect that is seated and retained in a connector using a number of bumpletts arranged in the system to exert a cam force that encourages retention of the interconnect in the connector. The connector is coupled to a target board. The connector comprises a spacer nest and a pair of boards, such as printed circuit boards, that may contain electrical circuitry. The cam bumpletts may reside at the interconnect, or on either or both of the pair of boards of the connector.

Cam bumplett apparatus and system

One or more termination circuits or networks having compensation properties that are operative to reduce reflections occurring between a probe utilized by a test and measurement analyzer to test a device under test (DUT), such as an integrated circuit device, and the device under test itself are employed. The termination circuits are preferably small and less obtrusive than larger connectors and their compensation networking compensates for the connection of the probe to the DUT as well as connection of the cable from the probe to the analyzer performing the test and measurement function. The functionality of the termination circuits may be located at the DUT in a termination network connector or within the structure of the probe itself.

Single point probe structure and method

The present invention involves a configurable flip flop having a first data input node, a second data input node, and an output node. The configurable flip-flop includes an inverter coupled to the first data input node. Each of a plurality of configuration lines address a multiplexor and the flip-flop output node for selecting one of the first data input node, the second data input node, or an inverted first data input and coupling the selected one to a multiplexor output. A latch receives the multiplexor output and generates a gated output and an edge triggered output. A configuration bit controlled selector couples either the gated output or the edge triggered output to the configurable flip-flop output node.

Configurable multifunction flip-flop

The present invention involves a configurable flip flop having a first data input node, a second data input node, and an output node. The configurable flip-flop includes an inverter coupled to the first data input node. Each of a plurality of configuration lines address a multiplexor and the flip-flop output node for selecting one of the first data input node, the second data input node, or an inverted first data input and coupling the selected one to a multiplexor output A latch receives the multiplexor output and generates a gated output and an edge triggered output. A configuration bit controlled selector couples either the gated output or the edge triggered output to the configurable flip-flop output node.

A software debugging analyzer nonintrusively acquires data concerning the execution of software on a real-time basis. Low-level event recognition is accomplished with programmable comparators, whose outputs are fed to high-level recognition comparators to define complex events. Dynamic recognition is provided by recognition cmparators programmable on a real time basis as variables are actuated. Acquired data is stored in memory in either a sequential or random access mode. A microprocessor translates high level commands into event constructs and processes the acquired data into a format suitable for display to a user.

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Colorado Springs, CO, United States of America

Kevin M Hall