Advanced Micro Devices Corporation

Kevin M Gillespie

Maurice B Steinman

Spencer Montgomery Gold

Guhan Krishnan

Bill K C Kwan

Donald A Priore

Dwight K Elvey

Joseph R Siegel

Harry R Fair

Timothy J Correia

A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.

Fault tolerant scannable glitch latch

A method, implemented in a processor, of determining a likelihood of failure of a circuit to be made in accordance with a circuit design, and a computer-readable storage medium storing instructions to the processor for carrying out the method. A sensitivity of a figure of merit to each variable of a plurality of variables is determined by simulating operation of the circuit using the processor. Determining the sensitivity is based on a departure of each of the variables from a respective mean value, where the variables include at least one variable derived from measurements of a fabricated component or component combination to be included in the circuit. Results from the simulation are used to predict a failure probability of the circuit to be made in accordance with the circuit design.

Method for analyzing sensitivity and failure probability of a circuit

Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.

Clock domain data transfer device and methods thereof

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Pembroke, MA, United States of America

Kevin M Gillespie