Sandisk Corporation

Sandisk Technologies Inc.

Everspin Technologies, Inc.

Clevx, LLC

Corsair Memory, Inc.

Innovative Memory Systems, Inc.

Longitude Flash Memory Systems S.à R.l.

Kevin M Conley

Carlos J Gonzalez

John S Mangan

Jeffrey G Craig

Daniel C Guterman

Yoram Cedar

Sergey Anatolievich Gorobets

Yigal Brandman

Geoffrey Steven Gongwer

Reuven Elhamias

Eran Sharon

Eli Harari

Idan Alrod

Raul-Adrian Cernea

Robert C Chang

Shahzad Khalid

Peter John Smith

Richard T Simko

Joel Bernard Jacobs

Alan Welsh Sinclair

Robert C Miller

Robert Andrew Howard

Jason T Lin

Jeff Salazar

Wesley G Brewer

Jason Patrick Hanlon

Jonathan J Hubert

Daniel Francis Kennedy

Charles Michael Schroter

Matt Peterson

Michael Alan Morganstern

Milton Lourenco Barrocas

Sanjay Dave

Mark Sompel

Sanjeev Aggarwal

Lev M Bolotin

Robert B Hubler

Alan David Bennett

Rotem Sela

Fabrice Jogand-Coulomb

Sarin A Deshpande

Simon B Johnson

Jason A Janesky

Jijun Sun

Raul Adrian Cernea

Michael Holtzman

Chi-Ming Wang

Ron Barzilai

Suresh Kumar Upadhyayula

Frederick B Mancoff

Yishai Kagan

Sumio Ikegawa

Noam Kedem

Avraham Shmuel

Eric Bone

John Beekley

Yong Wang

Daniel Schreiber

Richard C Spence

Jean-Christophe Klein

Wes G Brewer

E Earle Thompson

Philip D Royall

Lu Hui

James Carlton

Andrew J Paul

Gary Bordenkircher

Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.

Stacked magnetoresistive structures and methods therefor

A magnetoresistive device may include multiple magnetic tunnel junction (MTJ) stacks separated from each other by one or more dielectric material layers and electrically conductive vias extending through the one more dielectric material layers. Each MTJ stack may include multiple MTJ bits arranged one on top of another and the electrically conductive vias may be configured to electrically access each MTJ bit of the multiple MTJ stacks.

Magnetoresistive stacks and methods therefor

A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

Rewritable multibit non-volatile memory with soft decode optimization

A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

Flash controller cache architecture

A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone boundaries are adjusted to accommodate defects allowed by memory test to improve card yields and to adjust boundaries in the field to extend the usable lifetime of the card. Firmware scans for the presence of defective blocks on the card. Once the locations of these blocks are known, the firmware calculates the zone boundaries in such a way that good blocks are equally distributed among the zones. Since the number of good blocks meets the card test criteria by the memory test criteria, defects will reduce card yield fallout. The controller can perform dynamic boundary adjustments. When defects occur, the controller can perform the analysis again and, if needed, redistributes the zone boundaries, moving any user data.

Zone boundary adjustments for defects in non-volatile memories

A digital system including flash memory, coupled to a system-on-a-chip within which a flash memory subsystem controller is embedded, is disclosed. The system-on-a-chip includes support for a standard external interface, such as a Universal Serial Bus (USB) or IEEE 1394 interface, to which a host system such as flash memory test equipment can connect. Initialization of the flash memory is effected by opening a communications channel between the host system and the embedded flash memory subsystem controller. The host system can then effect initialization of the flash memory subsystem, including formatting of the flash memory arrays, loading application programs, and the like, over the communications channel.

Initialization of flash storage via an embedded controller

The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.

Pipelined data relocation and improved chip architectures

A method for using time from a trusted host device is disclosed. In one embodiment, an application on a memory device receives a request to perform a time-based operation from an entity authenticated by the memory device, wherein the entity is running on a host device. The application selects time from the host device instead of time from a time module on the memory device to perform the time-based operation and uses the time from the host device to perform the time-based operation. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Method for using time from a trusted host device

A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks

A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. Updated pages from multiple blocks are programmed into this other block in an order that does not necessarily correspond with their original address offsets. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made. The memory controller can dynamically create and operate these other blocks in response to usage by the host of the memory system.

Management of non-volatile memory systems having large erase blocks

A method for playing digital media files with a digital media player using a plurality of playlists is disclosed. One embodiment uses a plurality of playlists&#x2014;instead of a single playlist&#x2014;to reference a given pool of digital media files. After the songs of one playlist have been played, another playlist is selected, and songs from that playlist are played. Since the playlist selection is automatically made by the digital media player while it is offline, a fresh listening experience is created without requiring the user to connect the digital media player to the Internet. Preferably, each playlist is purposefully curated to ensure that the play order keeps the experience commensurate with a particular brand message.

Method for playing digital media files with a digital media player using a plurality of playlists

The present invention presents methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural examples are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.

Techniques for managing data in a non-volatile memory system (e.g., Flash Memory) are disclosed. A controller can use information relating to a host's file system, which is stored by the host on non-volatile memory, to determine if one or more clusters (or sectors with clusters) are currently allocated. The controller can use the information relating to the host's file system to identify when the host is sending data to the next free cluster and to store such data in a sequential format by copying data from other locations in the non-volatile memory.

FAT analysis for optimized sequential cluster management

Growing community of inventors

San Jose, TX, United States of America

Kevin M Conley