Lockheed Martin Corporation

Howard IP Law Group, Pc

Kevin L Robinson

Larry Charles Witkowski

Ming-Yih Kao

Kenneth R Boswell

William Hullinger Huber

Paul Saunier

Hua-Quen Tserng

Blake A Carnahan

Earl L Turner

A circuit assembly includes a sealable enclosure and at least one electronic circuit element contained within the sealable enclosure. The at least one electronic circuit element includes a control circuit, a garnet, and a first polymer material applied on a surface of the control circuit and on a surface of the garnet. A second polymer material fills a remaining space defined within the enclosure, the second polymer material applied on an exposed surface of the first material.

Corona prevention in high power circulators

A method for preventing corona effects in an electronic circuit comprising applying a coating of a first material to a surface of the electronic circuit, and applying a second material having a dielectric constant that is lower than that of the first material on an exposed surface of the first material, wherein the second material comprises a solid dielectric.

A harmonic trap filter suppresses at least one harmonic signal produced by an amplifier and includes an input terminal and a ground terminal. The harmonic trap filter further includes a plurality of resonators electrically coupled one to another between the input terminal and the ground terminal in a spatial order defined by relative phase shift of alternating voltage bias signals respectively applied thereto. The resonators are tuned to resonate at a frequency at which a phase delay is imparted to the at least one harmonic signal by the resonators to effect cancelation of the at least one harmonic signal at the input terminal.

Harmonic trap filter using coupled resonators

A method for preventing corona effects in an electronic circuit comprising the steps of applying a parylene coating to a surface of the electronic circuit, and applying a polyalphaolefin dielectric oil having a dielectric constant that is lower than that of the parylene coating on an exposed surface of the first material.

Corona prevention in radio frequency circuits

Corona effect in a monolithic microwave integrated circuit (MMIC) is prevented by disposing a bottom metal layer on a substrate, defining a conductive via through the substrate electrically contacting the bottom metal layer, the conductive via further connected to a reference electrical potential, disposing a layer of dielectric material on a region of the bottom metal layer, forming a component metal layer over the conductive via and in electrical communication with the via and the bottom metal layer to define an electrical component, forming a top metal layer on the layer of dielectric material, the layer of dielectric layer interposed between the top metal layer and the bottom metal layer to thereby define an MMIC capacitor on the substrate, the top metal layer of the MMIC capacitor being separated from the electrical component, and disposing a passivation layer adjacent and conformal to a side wall of the top metal layer.

Method for prevention of corona effect in a monolithic microwave integrated circuit (MMIC)

This invention pertains to a lightweight dual-band electronically steered phased array antenna having a multi-layer circuit for supplying DC and a ground plane to RF-on-flex subarrays. A dipole and two additional legs form a four-legged pyramid that stiffens the multi-layer circuit structure and serves as a bonding point to a radome surface. Two of the legs of the pyramid incorporate a low-band V dipole-radiating element. A third leg of the pyramid distributes RF energy to the subarrays via the multi-layer circuit. At the base of the pyramid is an open rectangular frame that accepts the insertion of the multi-layer circuit. An infrared laser transmitter distributes high and low band transmit/receive module control signals to an infrared detector on the opposite side of the subarrays.

Lightweight dual band active electronically steered array

The present invention is drawn to an MMIC capacitor comprising a dielectric material interposed between a metal top plate and a metal bottom plate; and a passivation layer having the composition of the dielectric material and applied to the capacitor components such that thickness of the layer eliminates a corona effect. The invention also includes a method for passivating a layer of SiN material onto a top plate having a thickness sufficient to reduce a corona effect dependent on an applied voltage.

Corona prevention in high power MMICs

A traveling wave device employs an active Gallium Nitride FET. The Gallium Nitride FET has a plurality of gate feeding fingers connecting to an input gate transmission line. The FET has a drain electrode connected to an output drain transmission line with the source electrode connected to a point of reference potential. The input and output transmission lines are terminated with terminating impedances which are not matched to the gate and drain transmission lines. The use of Gallium Nitride enables the terminating impedance to be at much higher levels than in the prior art. The use of Gallium Nitride permits multiple devices to be employed, thus resulting in higher gain amplifiers with higher voltage operation and higher frequency operation. A cascode traveling wave amplifier employing GaN FETs is also described having high gain and bandwidth.

Gallium nitride traveling wave structures

A semiconductor device including at least one gate terminal in operational contact with an active layer or top surface of the semiconductor substrate includes a deposited layer of boron phosphide covering the gate terminal and at least a portion of the active layer or the top surface next to and extending from the gate terminal. According to an aspect, the layer of boron phosphide is deposited by a chemical vapor deposition (CVD) process. The boron phosphide layer will have a thickness less than or equal to about 10 microns. The boron phosphide provides a heat spreading coating across the die surface, thus increasing the surface area that conducts the heat from the die. Since the boron phosphide coating is in intimate contact with the gate terminal(s) and the immediately adjacent passivation surfaces of the device, generated heat can rapidly spread away from the active junction or channel. The additional thermal path(s) provided by the boron phosphide coating may terminate away from the active region to further conduct away the heat through thermally unused areas of the device.

Topside thermal management of semiconductor devices using boron phosphide contacting a gate terminal

A circuit including: at least one radio frequency microstrip conductor; and, a least one vanadium oxide region electrically coupled to the at least one radio frequency microstrip conductor; wherein, the at least one vanadium oxide region is substantially conductive in a first temperature range, and substantially non-conductive in a second temperature range.

Vanadium oxide RF/microwave integrated switch suitable for use with phased array radar antenna

A circuit including: at least one conductor; a least one vanadium oxide region electrically coupled to the at least one conductor; and, at least one thermionic cooler thermally coupled to the vanadium oxide region; wherein, the thermionic cooler is suitable for transitioning the at least one vanadium oxide region from a first temperature range where the at least one vanadium oxide region is substantially conductive to a second temperature range where the at least one vanadium oxide region is substantially non-conductive.

Switch apparatus

A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Method for fabrication of devices in a multi-layer structure

The electrical length of an antenna element is modified by depositing on a top surface of a voltage variable dielectric a first conductor pattern. The identical conductor pattern is also deposited on a bottom surface of the dielectric layer. The dielectric layer is tunable and the structure is a sandwich with two identical conductors on top and bottom of a tunable dielectric area. The sandwich is created in the same shape as a planar spiral or logarithmic spiral and a DC electric field is applied between the conductors that control the dielectric constant and hence the electrical length of the antenna element.

Tunable antenna apparatus

The present invention comprises an integrated circuit fabricated on a single substrate where the integrated circuit comprises a first block comprising an enhancement mode pHEMT transistor on a substrate; a second block comprising a depletion mode pHEMT transistor on the substrate, the second block operatively connected to the first block; and a third block comprising a power pHEMT transistor on the substrate, the third block operatively connected to at least one of the first block and the second block. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope of meaning of the claims.

Electronic device comprising enhancement mode pHEMT devices, depletion mode pHEMT devices, and power pHEMT devices on a single substrate and method of creation

A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

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Clay, NY, United States of America

Kevin L Robinson