Lsi Logic Corporation

Kevin L Daberkow

Trung T Nguyen

Hidetaka Magoshi

Robert L Caulk, Jr

Randy E Bach

Henry Yang

A microprocessor system includes a core CPU for instruction execution and a coprocessor interconnected with said core CPU for system control and exception processing. The coprocessor includes a plurality of exception handling registers including an exception program counter having a restart location stored therein for use after an exception is serviced, a status register having operating mode identification and interrupt enabling bits, and a configuration and cache control register. Interrupt processing is compatible with a plurality of instruction sets with a particular instruction set being designated by setting at least one bit in the configuration and cache control register. Registers are provided to save the operating state of the CPU prior to interrupt enable, the operating state of the CPU being restored after exception processing is completed and user mode is reestablished.

Exception processing in superscalar microprocessor

The present invention concerns a method for eliminating or reducing clock skew introduced by differing signal propagation delays across a data bus. At high bus clock frequencies the time delay differences caused by path length differences can be catastrophic and must be eliminated by expensive layout techniques. An input/output (I/O) architecture is proposed here which tailors a delay to each individual data line, and thereby aligns all the incoming data. Furthermore, a clock signal is provided to indicate the optimal data sampling time. In the described embodiment, this circuit enables the transmission of four 32 bit words in parallel in one clock cycle of a 250 MHz processor.

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Fremont, CA, United States of America

Kevin L Daberkow