Medtronic, Inc.

Stmicroelectronics Gmbh

Stmicroelectronics S.a.

Medtronics, Inc.

Kevin K Walsh

Jeffrey David Wilkinson

Larry Earl Tyler

David C McClure

Mark A Lysinger

Paul F Gerrish

Robert W Hocken, Jr

Melvin P Roberts

Paul B Patterson

Glen W Benton

David L Thompson

James D Reinke

Paul J Huelskamp

John Charles Stroebel

Paul R Solheim

Javaid Masoud

Charles R Gordon

Todd A Kallmyer

Francois Jacquet

Jerry D Reiland

James H Ericksen

François Jacquet

Robert D Musto

Mark A Stockburger

Duane R Bigelow

Xander Evers

Roman Korsunsky

Brandon P Scott

Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array.

Memory array with flash and random access memory and method therefor, reading data from the flash memory without storing the data in the random access memory

An integrated circuit includes a clock tree network that distributes a clock signal to a plurality of clocked components of the integrated circuit. The clock tree network includes clock lines, each of which includes a clock tree delay element that provides a modified clock signal that is provided to an individual one the clocked components. Among the plurality of clocked components, one or more of the clocked components provides a data signal to another one or more of the clocked components. The one or more clocked components are configured having a transmission duration for the data signal that is longer relative to a transmission duration of the modified clock signal of the receiving clocked component.

Implantable medical device having clock tree network with reduced power consumption

Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.

Voltage mode sensing for low power flash memory

Random access memory having a plurality of memory cells, each of the plurality of memory cells having a memory element and a first electrical characteristic being variable based, at least in part, on temperature and a bias circuit operatively coupled to at least one of the plurality of memory cells, the bias circuit being configured to generate a bias voltage for the at least one of the plurality of memory cells. The bias circuit has a second electrical characteristic being variable based, at least in part, on temperature. The first electrical characteristic is approximately proportional to the second electrical characteristic over a predetermined range of temperatures, the predetermined range of temperatures being greater than zero. The bias voltage on each of the plurality of memory cells is approximately proportional with variations in the first electrical characteristic over the predetermined range of temperatures.

Stable memory source bias over temperature and method

Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.

Flash memory with integrated ROM memory cells

Techniques for generating timing constraints for an integrated circuit including a clock tree network are described. The techniques may be associated with a clock tree synthesis tool that receives a design of the integrated circuit and generates a clock tree network including a plurality of clocked components of the integrated circuit. The constraints may be generated as a function of the duration of propagation of a data signal from a transmitting clocked component coupled to a receiving clocked component.

Tool for evaluating clock tree timing and clocked component selection

An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Robust SRAM memory cell capacitor plate voltage generator

A bus system is provided for implantable medical devices. The bus system provides for flexible and reliable communication between subsystems in an implantable medical device. The bus system facilitates a wide variety of communications between various subsystems. These various subsystems can include one or more sensing devices, processors, data storage devices, patient alert devices, power management devices, signal processing and other devices implemented to perform a variety of different functions.

Implantable medical device bus system and method

Cyclic redundancy calculations are provided by operating on a data stream, e.g., a data stream in an implantable medical device, to perform a polynomial division thereon using one of a first cyclic redundancy code generator polynomial and a second cyclic redundancy code generator polynomial. The first cyclic redundancy code generator polynomial is a higher order polynomial than the second cyclic redundancy code generator polynomial and contains all terms of the second cyclic redundancy code generator polynomial. The polynomial division may be implemented using linear feedback shift register circuitry and circuitry to select between the use of the first or second cyclic redundancy code generator polynomial.

Cyclic redundancy calculation circuitry for use in medical devices and methods regarding same

A method and apparatus including conditional add and conditional add/subtract instructions are provided for use in the instruction set of a medical device instruction processor. More specifically, the conditional add and add/subtract instructions are provided to add two operands if a predetermined condition is satisfied within the instruction processor hardware. Additionally, the conditional add/subtract instruction may be used to subtract one operand from another operand if the predetermined condition is not satisfied. These instructions are adapted for use in implementing an efficient, interruptible, firmware-controlled multiplication or division mechanism. The inventive system allows multiplication or division operations to be interrupted at various intermediate points during the multiplication or division operation to thereby reducing interrupt latency.

Interruptable multiply and/or divide operations for use with an interrupt in a medical device processor

A signal processor operates on a microprocessor or state machine based system to ensure that the central processing unit (CPU) and pulse generator (PG) have finished their instructions before allowing a new transition on the system master clock. The CPU and PG contain circuitry which allows them to indicate when they are busy. These signals are fed to the signal processor to indicate when the CPU and PG are ready to start another instruction. The signal processor functions to prevent a noise glitch on the system clock from causing another operation to start before the one in process has finished. The output of the signal processor becomes the master clock signal used by the system.

Signal processor with intelligent feedback to ensure functionality of microprocessor and state machine based programmable pulse generators in the presence of clock and power supply disturbances

A peripheral memory patch apparatus for attachment to a patient's skin includes a high capacity memory for storing physiologic data uplinked from an implantable medical device. A resilient substrate provides support for a memory, microprocessor, receiver, and other electronic components. The substrate flexes in a complimentary manner in response to a patient's body movements. The substrate is affixed to the patient's skin with the use of an adhesive which provides for comfort and wearability. The low profile peripheral patch apparatus is preferably similar in size and shape to a standard bandage, and may be attached to the patient's skin in an inconspicuous location. A status indicator provides for a visual, verbal, or tactile indication of the operational status of the peripheral memory patch. Uplinking of physiologic telemetry data from the internal memory of an implantable medical device to the peripheral memory patch is initiated in response to a transfer signal produced by the peripheral memory patch. The transfer signal may be generated by the implantable medical device or upon actuation of a switch by the patient. Various telemetry techniques including radio frequency, acoustic, and body bus telemetry techniques, may be employed to transfer information between the implantable medical device and the peripheral memory patch.

Growing community of inventors

Peoria, AZ, United States of America

Kevin K Walsh