Globalfoundries U.S. Inc.

International Business Machines Corporation

Globalfoundries Inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Kevin K Dezfulian

Yusheng Bian

Karen A Nummy

Kenneth John Giewont

Huilong Zhu

Zhijiong Luo

Jeanne P Bickford

Clement Hsingjen Wann

Cyril Cabral, Jr

Christian Lavoie

Brian Joseph Greene

Rajarao Jammy

Chun-Yung Sung

Erik L Hedberg

Yung Fu Chong

Sunfei Fang

Michal Rakowski

Bo Peng

Hung Y Ng

Scott D Allen

Judson Robert Holt

Roderick Alan Augur

Susan K Lichtensteiger

Massimo Sorbara

Thomas F Houghton

Troy Joseph Perry

Abdelsalam A Aboketaf

Keith Donegan

Venkata Narayana Rao Vanukuru

Shuren Hu

Takako Hirokawa

Francis Afzal

Asli Sahin

Jeanne H Raymond

David B Riggs

Thomas Houghton

Aurelius L Graninger

Prateek Kumar Sharma

Carrie Yurkon

Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.

Calibration markers for a photonics chip

Structures for a waveguide escalator and methods of forming such structures. A structure comprises a first waveguide core, and a back-end-of-line stack including a first dielectric layer, a second dielectric layer on the first dielectric layer, an opening in the second dielectric layer, a second waveguide core including a section that overlaps with a section of the first waveguide core, and a plurality of third waveguide cores disposed between the section of the first waveguide core and the section of the second waveguide core. The plurality of third waveguide cores are positioned inside the opening in the second dielectric layer, the first dielectric layer comprises a first material with a first refractive index, and the second dielectric layer comprises a second material with a second refractive index different from the first refractive index.

Waveguide escalators for a photonics chip

Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.

Inductors with airgap electrical isolation

Structures including an electro-optical phase shifter and methods of fabricating a structure including an electro-optical phase shifter. The structure includes a waveguide core on a semiconductor substrate, and an interconnect structure over the waveguide core and the semiconductor substrate. The waveguide core includes a phase shifter, and the interconnect structure includes a slotted shield and a transmission line coupled to the phase shifter. The slotted shield includes segments that are separated by slots. The slotted shield is positioned between the transmission line and the substrate.

Slotted shields for use with an electro-optical phase shifter

Structures including a waveguide core and methods of fabricating a structure including a waveguide core. The structure comprises a photonics chip including a first chip region, a second chip region, a first waveguide core in the first chip region, and a second waveguide core in the second chip region. The first chip region adjoins the second chip region along a boundary. The first waveguide core includes a first tapered section, and the second waveguide core includes a second tapered section positioned across the boundary from the first tapered section. The first tapered section has a first width dimension that increases with increasing distance from the boundary, and the second tapered section has a second width dimension that increases with increasing distance from the boundary.

Photonics chips with reticle stitching by back-to-back tapered sections

Structures for an optical power modulator and methods of fabricating a structure for an optical power modulator. A first waveguide core includes first and second sections. A second waveguide core includes a first section laterally adjacent to the first section of the first waveguide core and a second section laterally adjacent to the second section of the first waveguide core. An interconnect structure is formed over the first waveguide core and the second waveguide core. The interconnect structure includes first and second transmission lines. The first transmission line is physically connected within the interconnect structure to the first section of the first waveguide core. The second transmission line includes a first section physically connected within the interconnect structure to the second section of the first waveguide core and a second section adjacent to the first transmission line.

Optical power modulators with unloaded transmission lines

Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a dielectric layer including an edge, a waveguide core region on the dielectric layer, and multiple segments on the dielectric layer. The waveguide core region has an end surface, and the waveguide core region is lengthwise tapered toward the end surface. The segments are positioned between the waveguide core region and the edge of the dielectric layer. A waveguide core has a section positioned over the waveguide core region in an overlapping arrangement. The waveguide core has an end surface, and the section of the waveguide core is lengthwise tapered toward the end surface.

Hybrid edge couplers with layers in multiple levels

A photonics integrated circuit includes a semiconductor substrate; a buried insulator layer positioned over the semiconductor substrate; and a back-end-of-line (BEOL) insulator stack over a first portion of the buried insulator layer. In addition, the PIC includes a silicon nitride (SiN) waveguide edge coupler positioned in a first region over the buried insulator layer and at least partially under the BEOL insulator stack. An oxide layer extends over a side of the BEOL insulator stack. The SiN waveguide edge coupler provides better power handling and fabrication tolerance than silicon waveguide edge couplers, despite the location under various BEOL layers. The PIC can also include silicon waveguide edger coupler(s).

Photonics integrated circuit with silicon nitride waveguide edge coupler

Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The edge coupler includes a waveguide core, and a shaped layer is positioned over a portion of the waveguide core. The waveguide core is comprised of a first material, and the shaped layer is comprised of a second material different in composition from the first material. The first material may be, for example, single-crystal silicon, and the second material may be, for example, silicon nitride.

Edge couplers with stacked layering

Structures for a filter and methods of fabricating a structure for a filter. The filter is coupled to a waveguide core. The filter includes a first plurality of grating structures positioned adjacent to a first section of the waveguide core and a second plurality of grating structures positioned adjacent to a second section of the waveguide core. The first plurality of grating structures are configured to cause laser light in a first portion of a wavelength band to be transferred between the first section of the waveguide core and the first plurality of grating structures. The second plurality of grating structures are configured to cause laser light in a second portion of a wavelength band to be transferred between the second section of the waveguide core and the second plurality of grating structures.

Grating-based filters for photonics applications

Methods and structures for leakage screening are disclosed. A method includes sorting devices manufactured from the same device design into voltage bins corresponding to a respective supply voltage. The method further includes determining a respective total power of each of the voltage bins. The method further includes determining a respective uplift power of the voltage bins. The method further includes determining a respective first leakage screen value for each of the voltage bins based on the respective uplift power of each of the voltage bins.

Selective voltage binning leakage screen

Methods and systems for multiple manufacturing line qualification are provided. A method includes establishing a product template and producing products on one or more manufacturing lines. The products include product macros placed on a chip. The method also includes establishing allowed parametric match from line to line. The method further includes determining that products from the one or more manufacturing lines meet the allowed parametric match.

Multiple manufacturing line qualification

Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.

Systems and methods for semiconductor line scribe line centering

An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors

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Mount Kisco, NY, United States of America

Kevin K Dezfulian