Motorola Corporation

Semiconductor Components Industries, LLC

Kevin Joseph Jurek

Lalit O Patel

William Oliver Mathes

Philip Alan Jeffery

Timothy Ernest Seneff

A receiver circuit () includes a first gate () that receives an input signal (V, V) and has an output () for providing an output signal (V, V). A shifting circuit () is coupled for shifting the common mode potential of the input signal to produce a shifted signal (V, V). A second gate () has an input () that receives the shifted signal and an output coupled to the output of the first gate.

High speed receiver with wide input voltage range

In one embodiment, a bipolar cell () includes a cell boundary () that defines a cell active area (), a first array of bipolar transistors () is formed within the cell active area () and configured for a first function. The bipolar transistors () within the first array () are parallel to each other. The bipolar cell () further includes a second array of bipolar transistors () formed within the cell active area () and configured for a second function that is different than the first function. The bipolar transistors () within the second array () are parallel to each other and oriented in a different direction than the transistors () in the first array ().

Cell structure for bipolar integrated circuits and method

A multiplexer output cell (FIG. ) controls the operation of multiplexer input cells ( ) in a multistage multiplexer according to the value of a signal select input ( ), and a state control input ( ). A signal driver ( ) having a number of logical outputs comparable to the number of stages in the multiplexer is used in conjunction with the state control signal ( ) to control the power ON/OFF state of each cell in the multiplexer. The multiplexer input and output cells ( ) which are in the signal path are set to a power ON condition, while the multiplexer input and output cells ( ) which are not in the signal path are set to a power OFF position. In this manner, only those cells which are in the signal path are powered ON, resulting in significant power savings.

Reduced power consumption multiplexer using self-decoding power down logic

A method and apparatus for controlling current flow in current sources includes a current source FET (18), a control FET (20), and a driver circuit which includes complementary logic (310). The use of complementary logic for control advantageausly allows commonly available logic functions to control the current flow in individual current sources while maintaining a substantially constant bias voltage on the gate of the current source FETs. A chip-wide bias generator can be maintained substantially constant while controlling individual current sources.

Growing community of inventors

Gilbert, AZ, United States of America

Kevin Joseph Jurek