Lucent Technologies Inc.

At+t Corp.

Kevin John O'Connor

Robert Charles Frye

Yee Leng Low

Mark Richard Pinto

Jeffrey Devin Bude

With shrinking dimensions, and closely spaced runners, capacitive coupling between bitlines in dual port SRAMS becomes an important design issue. Techniques for reducing that coupling are described. A shielding runner placed between the read and write bitlines and tied to V.sub.DD or V.sub.SS substantially reduces unwanted crosstalk. Word lines can be similarly isolated.

Shielded bitlines for static RAMs

The specification describes interconnection layouts for chip-on-chip packages using solder bump interchip connections as vias between a single level metal interconnection pattern on the lower support IC chip and another single level interconnection pattern on the upper IC chip. This arrangement allows for the formation of air isolated crossovers of features on either chip.

Chip-on-chip IC packages

The invention is directed to a memory cell with a floating gate and a method for charging the floating gate using channel-initiated secondary electron injection (CISEI). In the device of the present invention, a positive bias voltage of about 1.1 volts to about 3.3 volts is applied between the drain and the source when introducing charge onto the floating gate. A negative bias voltage of about -0.5 volts or more negative is applied to the substrate and the source. The drain substrate bias induces a sufficient amount of secondary hot electrons to be formed with a sufficient amount of energy to overcome the energy barrier between the substrate and the floating gate to charge the floating gate.

Method and apparatus for hot carrier injection

Each memory cell in an SRAM array contains an auxiliary reading transistor connected across one of the transistors in each cell. A row read line controls the ON-OFF condition of this auxiliary reading transistor. In addition, each cell has two access transistors for connecting the cell to complementary column bit lines The ON-OFF condition of both of these access transistors is controlled by a row write line. Each cell has two power nodes, one connected to a power source such as VDD and the other connected to a column detector line that terminates in a current sensor. The state of the memory cell is sensed by this current sensor. In one embodiment, the power line that brings the voltage VDD to the cells is a column line; in another embodiment, it is a row line. Thus there are a total of four column lines and two row lines in the one embodiment, and a total of three column lines and three row lines in the other embodiment.

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Lebanon, NJ, United States of America

Kevin John O'Connor