Qualcomm Incorporated

Kevin Jaget

James Norris Dieffenderfer

Rodney Wayne Smith

Thomas Philip Speier

Brian Stempel

Michael W Morrow

Manish Garg

Yusuf Cagatay Tekmen

Pritha Ghoshal

Harsh Thakker

Sang Hoon Lee

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Combining load or store instructions

Growing community of inventors

Raleigh, NC, United States of America

Kevin Jaget