Micron Technology Incorporated

Round Rock Research, LLC

Other

Kevin J Torek

Whonchee Lee

Kevin R Shea

Satish Bedge

Donald L Yates

Li Li

Paul A Morgan

Scott E Sills

Kamal M Karda

Mark Fischer

Todd R Abbott

Robert J Hanson

Niraj B Rana

Yi Fang Lee

Sandra Tagg

Amy Weatherly

Gurtej S Sandhu

Anton J deVillers

Garo Jacques Derderian

Zhiping Yin

Thomas M Graettinger

Donald L Westmoreland

Si-Woo Lee

Scott L Light

Janos Fucsko

Hongqi Li

Sukesh Sandhu

Terrence B McDaniel

Alex J Schrinsky

Chris W Hill

Lars P Heineck

Jaydip Guha

Jin Lu

Richard C Hawthorne

Grady S Waldo

Ranjan Khurana

Gurpreet S Lugani

Sheng-Wei Yang

Thy Tran

Jonathan C Morgan

Richard C Hawthorne, Deceased

Yongjun Jeff Hu

Kyle K Kirby

Fatma Arzum Simsek-Ege

Michael L Nuttall

Max F Hineman

Prashant Raghu

Michael D Hyatt

David L Chapek

Shane J Trapp

Yoshiki Hishiro

Yunfei Gao

Kamal Kumar Muthukrishnan

David E Smith

James M Buntin

Gurpreet Lugani

An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

Array of vertical transistors and method used in forming an array of vertical transistors

A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

Methods of forming transistors and methods of forming devices comprising transistors

An apparatus includes at least one vertical transistor having a channel region. The channel region includes an upper region having a first width and a lower region below the upper region and having a second width smaller than the first width. The upper region defines at least one overhang portion extending laterally beyond the lower region. The at least one vertical transistor further includes gate electrodes at least partially vertically beneath the at least one overhang portion of the upper region of the channel region. Additional apparatuses and related systems and methods are also disclosed.

Apparatuses comprising vertical transistors having gate electrodes at least partially recessed within channel regions, and related methods and systems

Some embodiments include an integrated assembly which includes a base structure. The base structure includes a series of conductive structures which extend along a first direction. The conductive structures have steps which alternate with recessed regions along the first direction. Pillars of semiconductor material are over the steps. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The semiconductor material may be semiconductor oxide in some applications. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

Methods of forming semiconductor structures comprising thin film transistors including oxide semiconductors

Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.

Low capacitance interconnect structures and associated systems and methods

A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

Methods of forming capacitors

Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction. Portions of a second mask material underlying the first mask material at intersections of the first openings and second openings are removed to form holes in the second mask material and to expose a substrate underlying the second mask material.

Methods for forming semiconductor devices and semiconductor device structures

Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.

Subresolution silicon features and methods for forming the same

A method of forming a pattern on a substrate includes forming openings in material of a substrate. The openings are widened to join with immediately adjacent of the openings to form spaced pillars comprising the material after the widening. Other embodiments are disclosed.

Methods of forming a pattern on a substrate

A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Photoresist processing methods

Growing community of inventors

Meridian, ID, United States of America

Kevin J Torek