Itt Manufacturing Enterprises, Inc.

Exelis Inc.

Corrent Corporation

Kevin J Osugi

Richard J Takahashi

Nhu-Ha Yup

Lee Noehring

Bryan Doi

Darren L Parker

Michael Dean Collins

Michael D Collins

Darren Parker

Lee P Noehring

Architecture for embedding a cryptographic engine in a processor is disclosed. An ASIC processor is embedded with a programmable processing core, such as an FPGA, with the key register and I/O registers remaining in fixed logic.

Configurable ASIC-embedded cryptographic processing engine

A combination firmware and hardware cryptographic core architecture is provided for encrypting, decrypting and authenticating data. The core provides flexibility to change and add new cryptographic protocols, while providing increased performance by loading new firmware into a microcontroller that programs behavior of various components in the core. The core combines a microcontroller programmable by firmware, and flexible aligner, insertion and removal controllers programmed by the microcontroller that process, manage and manipulate an incoming data stream as it moves through the core. The firmware may be reprogrammed upon an enhancement or change to a protocol while still realizing performance benefits of the hardware. Reprogramming the microcontroller allows it to change the way the aligner, insertion and removal controllers manipulate the data stream as it enters various components. Such systems provide redesign time savings compared to hardware cryptographic core architectures, and improved speed and throughput compared to software cryptographic core architectures.

Method and system for cryptographic processing core

A firmware cipher component is provided which can be configured and programmed to efficiently implement a broad range of cryptographic ciphers while accelerating their processing. This firmware cipher component allows an ASIC to support multiple cipher algorithms while accelerating the operations beyond speeds conventionally achieved by software or firmware only solutions. This system combines cryptographic specific custom instructions with hardware based data manipulation accelerators. The cryptographic specific custom instructions and hardware accelerators may support both block and stream ciphers. Thus, the system may be reconfigured, allowing the cipher algorithm to change without halting the system. Further, embedding the Firmware Programmable Cipher within an ASIC may allow future capabilities to be supported in secure applications.

Method and system for embedded high performance reconfigurable firmware cipher

A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo product is post-processed to obtain the final result.

Circuit and method for performing multiple modulo mathematic operations

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Higley, AZ, United States of America

Kevin J Osugi