Analog Devices,inc.

Unitrode Corporation

Kevin J McCall

Janos Kovacs

David C Reynolds

Wyn T Palmer

Ronald Kroesen

Michael J Demler

George R Spaulding, Jr

A transconductance filter control system for compensating for drift in transconductance of a slave transconductance amplifier in a continuous time transconductance filter including: a master transconductance amplifier having an output which is a function of its transconductance and a control input for controlling the transconductance of the master transconductance amplifier; a tuning signal source for providing a tuning signal representative of a preselected characteristic of the transconductance filter; a comparing circuit, responsive to any deviation from a predetermined difference between the tuning signal and the output of the master transconductance amplifier, representative of a deviation of the transconductance of the master transconductance amplifier, for providing a compensation signal; and a circuit for applying the compensation signal to the control input of the master transconductance amplifier and to the control input of the slave transconductance amplifier in the transconductance filter to adjust the transconductance of both the master and slave transconductance amplifiers and restore the predetermined difference between the tuning signal and the output of the master transconductance amplifier.

Transconductance filter control system

A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.

Sampled delay locked loop insensitive to clock duty cycle

A programmable pulse slimmer system for a low pass ladder filter includes a filter input current source for providing to a low pass ladder filter the input signal to be filtered; and a high frequency boost current source for injecting into the low pass ladder filter forward of the first inductor device a high frequency load current which is a scaled inverse replica of the input signal to provide gain at the high frequency end of the low pass band of the low pass ladder filter.

Programmable pulse slimmer system for low pass ladder filter

A composite load circuit for use within another circuit includes at least one amplifying transistor. The composite load circuit includes first and second transistors connected in parallel. Each load transistor has a gate that receives a common control voltage. Each load transistor also has a different turn-on threshold voltage. A resistor, connected in parallel with the load transistors, limits an effective impedance of the load transistors.

Composite load circuit

According to embodiments of the present invention, a driver circuit, has first and second reference voltage rails for receiving first and second reference voltages, has first and second inputs for receiving an input differential signal and has first and second outputs for providing an output differential signal. The driver circuit comprises a first CMOS transistor, a second CMOS transistor, and first, second and third current sources. Positive voltage levels with respect to ground at the first and second outputs, are within typical acceptable ECL output voltage levels.

All-MOS differential high speed output driver for providing positive-ECL

A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

Dynamic phase selector phase locked loop circuit

A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

All-MOS precision differential delay line with delay a programmable

An all MOS single-ended to differential level converter including: first and second source follower circuits each including first and second PMOS semiconductors each having a drain, a source and a gate electrode; a current source commonly connected to the drain electrodes of the first and second PMOS semiconductors; an input circuit for providing to one of the gate electrodes a single-ended input signal and to the other an inverted single-ended input signal; and first and second load impedances connected to the source electrodes of the first and second PMOS semiconductors, respectively, for providing output analog differential signals at a level which is a function of the load impedances and current source magnitude.

All MOS single-ended to differential level converter

Auto-zeroing clocking signals, a first auto-zeroing clocking signal of comparatively-low frequency and duty cycle and a second auto-zeroing clocking signal of the same comparatively-low frequency but complementary and comparatively-high duty cycle, and a sampling clocking signal of comparatively-high frequency respectively initiate auto-zeroing of a circuit element subject to output offset error and data sampling of an A.C. input signal to a latch. The sampling of the A.C. input signal to the latch occurs at the comparatively-high frequency of the clocking signal during the 'on' time of the comparatively-high duty cycle second auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide higher speed sampling than heretofore possible. The auto-zeroing of the circuit element subject to input offset error occurs during the 'on' time of the comparatively-low duty cycle first auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide lower power sampling than heretofore possible. Typically, the circuit element is either an analog comparator or an operational amplifier, and the sampling circuit of the invention has exemplary utility in analog-to-digital (A/D) conversion.

Growing community of inventors

Leominster, MA, United States of America

Kevin J McCall