3com Corporation

Kevin J Hyland

Kevin Jennings

Vincent Gavin

Tadhg Creedon

Denise De Paor

Suzanne M Hughes

Mike Lardner

Brendan Walsh

Sean Boylan

Derek Coburn

A network switch which allows a network processor to process resultant data from a look-up engine while the look-up engine proceeds to deal with a subsequent packet. The look-up engine stores the resultant data in registers from which the resultant data is written back for the packet if the processor does not intervene. If the processor intervenes it acts on the resultant data, which is written back for the packet only after the processor has finished. A system of pointers and busy bits ensures that the packet is not forwarded until the look-up engine and (if required) the network processor have completed their operations in relation to the packet.

Network switch with parallel working of look-up engine and network processor

A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be 'off-chip'. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Automatic generation of interconnect logic components

An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Asic system architecture including data aggregation technique

Growing community of inventors

Dublin, Ireland

Kevin J Hyland