International Business Machines Corporation

Kevin J Gildea

Rama Krishna Govindaraju

Peter H Hochschild

Chulho Kim

Carl Alfred Bender

Gautam H Shah

Robert Sidney Blackmore

Paul D DiNicola

Jamshed H Mirza

Fu Chung Chang

Renato John Recio

Roger Gregory Hathorn

Mark Richard Nutter

Scott M Carlson

Jay Robert Herring

Catherine Helen Crawford

Aaron C Brown

Jeffrey William Palm

Richard A Swetz

Peter Kenneth Szwed

John Scott Houston

Piyush Chaudhary

Donald G Grice

Leonard W Helmer, Jr

Steven J Martin

Jason E Goscinski

Patricia E Heywood

Yun-Pong Huang

Rama J Govindaraju

Jaroslaw Nieplocha

A method and system of storing and retrieving data in a computer system are disclosed. In an embodiment, the method comprises storing a data object at a specified location in a first data store, storing in a second data store first information identifying said specified location, retrieving the data object from a defined location in the first data store, obtaining second information identifying the defined location in the first data store, and comparing the second information to the first information to determine if the first information and the second information identify a same location in the first data store. In embodiments of the invention, the method further comprises when the second information and the first information identify different locations in the first data store, generating a fault signal to indicate that the location of the data object in the first data store has changed.

Distributed client based cache for keys using demand fault invalidation

A network system supports multiple network communication protocols. In one embodiment, network device driver software provides a 'Fibre Channel over Ethernet' communication capability and methodology. Device driver software manages a Fibre Channel to Ethernet and Ethernet to Fibre Channel address translation in real time for data packet communications in the network system. Different embodiments of the disclosed network system include multiple name servers and network device driver software that together provide multiple adapter name discovery methodologies. In one embodiment, the adapter name discovery methodologies include port name discovery and adapter attributes discovery.

Method and apparatus for an adapter in a network device to discover its adapter name in a network system

A network system supports multiple network communication protocols. In one embodiment, network device driver software provides a 'Fiber Channel over Ethernet' communication capability and methodology. Device driver software manages a Fiber Channel to Ethernet and Ethernet to Fiber Channel address translation in real time for data packet communications in the network system. Different embodiments of the disclosed network system include multiple name servers and network device driver software that together provide multiple adapter name discovery methodologies. In one embodiment, the adapter name discovery methodologies include port name discovery and adapter attributes discovery.

Method and apparatus for enabling an adapter in a network device to discover the name of another adapter of another network device in a network system

In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Efficient probabilistic duplicate packet detector in computer networks

In a multinode data processing system in which nodes exchange information over a network or through a switch, a structure and mechanism is provided within the realm of Remote Direct Memory Access (RDMA) operations in which DMA operations are present on one side of the transfer but not the other. On the side in which the transfer is not carried out in DMA fashion, transfer processing is carried out under program control; this is in contrast to the transfer on the DMA side which is characteristically carried out in hardware. Usage of these combination processes is useful in programming situations where RDMA is carried out to or from contiguous locations in memory on one side and where memory locations on the other side is noncontiguous. This split mode of transfer is provided both for read and for write operations.

Half RDMA and half FIFO operations

An efficient mechanism for sending messages without the use of intermediate copies (i.e. without the staging of data) is provided. In particular an interface specification which allows use users of a transport protocol is defined so as to lend itself to efficient implementations. The interface specification is a complete and robust set of user functions usable within systems desiring reliable and efficient zero copy transport protocols. Two methods are provided to accomplish the implementation of an efficient zero copy protocol. The first method is especially useful in systems where the network device has limited capabilities in terms of hardware, message fragmentation and message reassembly. An additional RDRAM memory allows data to reside in an adapter while handshake operations take place between an adapter and a node so as to specify the final destination of the data. The second method takes advantage of network devices with advanced features which are exploited for maximum efficiency.

Mechanisms for efficient message passing with copy avoidance in a distributed system using advanced network devices

Mechanisms for efficient message passing with copy avoidance in a distributed system

Method, apparatus and program product for communicating from a node to a communications device. A Hardware Abstraction Layer (HAL) provides functions which can be called from user space in a node to access the communications device. An instance of HAL is created in the node. Device specific characteristics from the communications device and a pointer pointing to HAL functions for accessing the communications device are obtained by HAL. HAL then opens multiple ports on the communications device using the functions pointed to by the pointer, and messages are sent between the node and the communications device. The messages thus sent are optimized with respect to the communications device as determined by the obtained device specific characteristics. Multiple processes and protocol stacks may be associated with each port in a single instance of HAL. A further embodiment provides that multiple virtual ports may be associated with a port, with a multiple protocol stacks associated with each virtual port. A further embodiment provides that multiple communications devices may be associated with a single instance of HAL.

Hardware interface between a switch adapter and a communications

A method, apparatus and program product for detecting a communication event in a distributed parallel data processing system in which a message is sent from an origin to a target. A low-level application programming interface (LAPI) is provided which has an operation for associating a counter with a communication event to be detected. The LAPI increments the counter upon the occurrence of the communication event. The number in the counter is monitored, and when the number increases, the event is detected. A completion counter in the origin is associated with the completion of a message being sent from the origin to the target. When the message is completed, LAPI increments the completion counter such that monitoring the completion counter detects the completion of the message. The completion counter may be used to insure that a first message has been sent from the origin to the target and completed before a second message is sent.

Signaling communication events in a computer network

A method, apparatus and program product for message communication in a distributed parallel data processing system. A user message is sent from a sender to a receiver. The user message contains user data and a pointer to a header handler routine. The header handler routine includes a first pointer to a target user buffer and a second pointer to a completion routine. When the user message is received, a low level application program interface (LAPI) is informed which invokes the header handler routines which returns the first and second pointers. LAPI then transfers the user data to the user buffer indicated by the header handler routine, and invokes the completion routine indicated by the header handler routine to complete the transfer of the user message to the receiver.

Method and apparatus for efficient communications using active messages

A parallel multiprocessor data processing system having a plurality of nodes for processing data and a switch connected to each of said nodes for switching messages between the nodes, each node having a node processor for defining messages under program control to be sent to another node. Each of the nodes has an I/O processor for controlling the sending of messages to another node via the switch, and a shared memory which can be accessed by both the node processor and the I/O processor. Instructions for the messages to be sent by the I/O processor are stored in mailboxes in the shared memory by the node processor. A comparing circuit compares addresses on the bus to the contents of a plurality of address registers and sets the corresponding bit in a results register for each match. The adapter processor reads the contents of the results register such that the adapter processor may, with a single bus access, determine all mailboxes that have been accessed by the node processor.

Memory bus address snooper logic for determining memory activity without

A method and apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus. The FIFO buffer having a first port connected to the first bus and a second port connected to the second bus. The apparatus further includes a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch. The packets are communicated between the memory of the main processor and the switch in accordance with the communication protocol. The first and second DMA engines transfer data for the packets independently of each other.

Growing community of inventors

Bloomington, NY, United States of America

Kevin J Gildea