Texas Instruments Corporation

Kevin J Craig

Kenneth L Williams

M Dwayne Ward

A clocked first-in first-out (FIFO) memory includes interleaved dual-port static random access memories (SRAM's) 32 and 36. The FIFO has status flags 44 to indicate empty and full conditions and two programmable flags, almost full and almost empty, to indicate when a selected number of words is stored in memory. In accordance with the present invention, the FIFO has retransmit capability, allowing previously read data to be accessed again. The FIFO is put in retransmit mode by providing a retransmit mode (RTM) input signal. This event causes the current read address stored in the read address registers 52 and 54, the interleave status in toggle circuit 22, the data in the data output latches 18 and 20 and in the pipeline latch 42, and the status flags 44, to be saved in shadow registers 64, 66, 24, (30, 62, 70, 116 and 120. While the FIFO is in the retransmit mode, the occurrence of a Read From Mark input signal initiates the retransmit process, during which the saved read address count, output data and status flags are restored from their respective shadow registers, and the data from this restored starting point is retransmitted on the data out buffer 46. Data may be repeatedly retransmitted from the saved starting position. A new retransmit starting position may be selected after taking the FIFO out of retransmit mode by removing the RTM input signal.

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McKinney, TX, United States of America

Kevin J Craig