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Cadonca Design Systems, Inc.

Kevin Hwang

Jun Lu

Lin Yang

Yan Zhong

Yuwei Zhang

Shue-Lee Chang

A decision feedback equalizer is configured to equalize an input signal to generate a recovered output signal. Linear feed-forward filter circuitry is configured to provide a linearly filtered output signal based on the input signal. Composite trellis decoder circuitry configured to process a combined signal that is based on a combination of at least the linearly feed-forward filtered output signal and on output of linear or non-linear feedback filter circuitry, in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal, to provide a trellis-decoded output signal as input to the linear or non-linear feedback filter circuitry. The composite trellis decoder circuitry is further configured to provide a particular phase output of the combined signal, based on the state metrics, as the decoded output signal.

Decision feedback equalization with composite trellis slicer

Method and system for efficiently and quickly forming a sequence of convolution values from an over-sampled digital signal sequence. Convolution value differences are computable from a set of digital signal values that is smaller than the original set of signal values by a factor of R, the over-sampling rate. The number of adders and the associated time delay for computation of the convolution differences are reduced by at least a factor R and by at least a factor approximately proportional to log (R), respectively, as compared to conventional computation of a convolution value. This approach is used to estimate a time value for which the convolution attains a largest magnitude or value.

Low complexity multiple bits matched filter

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Cupertino, CA, United States of America

Kevin Hwang