Intel Corporation

Technology Inc. 64

Other

Standard Microsystems Corporation

Princeton Video Image, Inc.

Kevin Harney

David L Sprague

Allen H Simon

Michael J Keith

Eiichi Kowashi

Walter P Hays

Shih-Wei Shiue

George F Salem

Vitaly H Shilman

Anthony P Bertapelli

Nicola J Fedele

Gregory M Papadopoulos

Michael F Patti

Louis A Lippincott

Brian Astle

John M Keith

Michael Papadopoulos

Gary Loeser

Gregory House

Richard Wahler

Lawrence D Ryan

Gary J Lavelle

Tuan H Bui

Herbert Hudson Taylor, Jr

David Dea

Mike S Kelly

James L Jeffers

Anthony P Bertapellil

Dinesh G Rao

Michael Kelly

Gregory Michael Papadopoulos

Vitaly Haskel Shilman

George Francis Salem

Walter Patrick Hays

Anthony Paul Bertapelli

Allen Henry Simon

David Leroy Sprague

In one embodiment, a monitoring device (e.g., a slave device) may be configured to perform a plurality of monitoring functions. For example, the monitoring device may comprise a watchdog timer configured to monitor communications between the processing unit (e.g., a host processor) and the monitoring device. The watchdog timer may cause the monitoring device to enter a failsafe mode of operation if the processing unit fails to communicate with the monitoring device within a predetermined period of time. Additionally, the monitoring device may be configured to perform thermal management functions via one or more temperature sensors. The monitoring device may enter the failsafe mode of operation if a sensed temperature exceeds a predetermined temperature limit. Furthermore, the monitoring device may also comprise a status unit that is operable to provide the processing unit an indication of a state of the monitoring device.

Failsafe slave mechanism for mission critical applications

A system, method and computer program product for real-time insertion of indicia (e.g., an advertisement) into a live (or taped) broadcast. Typically, the invention allow insertion with occlusion onto surfaces such as tennis courts, the wall behind home plate on a baseball field, the grass or turf on a soccer or football stadium, and the like. The occlusion processing described herein can handle multiple colors in the background image during the insertion of the indicia into a video image. The invention can thus adapt to changing light conditions in the video image. The process includes obtaining a video image from a camera. The video image is typically digitized. Next, the pixels within the video image are sampled. A plurality of background colors are then identified for the sampled pixels. An opacity value is then assigned to each pixel in the indicia based on whether the color of a positionally corresponding pixel in the video image is the same color as one of the plurality of background colors. Finally, pixels within the indicia are displayed in the video image if the color of the positionally corresponding pixel in the video image is the same color as one of the background colors and a pixel in the indicia is not displayed in the video image if the positionally corresponding pixel in the video image is not the same color of as one of the background colors.

System and method for real time insertion into video with occlusion on areas containing multiple colors

A video processor system has separate and independent video processors for performing a variety of video processor functions required for encoding and decoding video signals. Each of the separate video processors performs its own individual set of video processor functions. During the encode process the first video processor performs motion estimation to provide motion estimation information which it applies to the second video processor. The second video processor receives the motion estimation information and performs forward and inverse discrete cosine transforms, quantization and dequantization, frame addition and frame differencing, as well as run length encoding. The run length encoding operation produces run/value pairs which are then applied to the first video processor. The first video processor performs variable length encoding upon the run/value pairs. During the decoding process the first video processor performs a variable length decode and applies the variable length decoded data to the second video processor. The second video processor performs run length decoding, dequantization, inverse discrete cosine transforms and frame addition according to the received variable length data. The inverse transformed data produced by this operation is then applied to the first video processor.

Task-splitting dual-processor system for motion estimation processing

A computer-implemented method for encoding image signals. According to a preferred embodiment of the invention, a plurality of search blocks is selected in accordance with the location of a reference block of a current frame. A plurality of words corresponding to the plurality of search blocks is read from a memory device. A difference measurement for each search block of the plurality of search blocks with respect to the reference block is determined from the plurality of words and from the reference block.

Motion estimation with efficient block matching

A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and for accessing a service routine in response to a page fault, are described. In one embodiment, the apparatus for translating comprises a processor; a page table having a translation mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive values in the comparison value register until a match comparison value is found. If a match comparison value is found, a programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress to provide the second address. If a match comparison value is not found, a fault interrupt is generated to interrupt the translation and the processor accesses a service routine in accordance with the fault interrupt.

Method and apparatus for translating addresses using mask and

A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as a system address space, are described. Data alignment signal determinations based on comparisons between destination and source addresses permit automatic replacement of virtual addresses with actual physical addresses to permit direct data transfer between devices. In one embodiment, the apparatus for translating comprises a processor; a page table having a mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive comparison values in the comparison value register until a match comparison value is found. A programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress. The programmable replacement values, which correspond to programable map windows, permit the programmable mapping of virtual addresses into different predetermined regions of system virtual address space.

A system and method is provided for encoding data wherein contiguous data values represent a video image. Three contiguous data values are applied to a loop filter to provide digital filtering of the data values. A frame differencing device performs a subtraction operation upon one of the three contiguous data values simultaneously with the performance of a filtering operation upon another one of the three contiguous data values. Additionally, a discrete cosine transform device performs transform operations upon the third contiguous data value simultaneously with the performance of the digital filtering and the frame differencing operation upon the other two contiguous data values. Because the loop filter is a multipass device the frame differencing device and the discrete cosine transform device must wait while some filtering operations are performed. As soon as one of the contiguous values is applied to the output of the digital filtering device it is operated upon by the frame differencing device. When the frame differencing device is done with this value the discrete cosine transform device begins operating upon the output of the frame differencing device and the frame differencing device operates on the next contiguous data value from the loop filter. A discrete cosine transform system is provided for performing discrete cosine transforms on matrices of input video data.

Pipelined video encoder architecture

A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to grant to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.

System for controlling arbitration using the memory request signal types

A method and apparatus for processing data. According to a preferred embodiment, the apparatus comprises a plurality of datapaths, each datapath comprising datapath processor, and a statistical decoder input channel device. The statistical decoder input channel device prefetches variable length encoded data from a variable length encoded data source in response to a request by a program running on a datapath processor of a datapath of the plurality of datapaths. The statistical decoder input channel device comprises a statistical decoder processor and memory for decoding the variable length encoded data to provide fixed length decoded data, and a transmission output channel for transmitting the fixed length decoded data to the datapath.

System with plurality of datapaths having dual-ported local memory

Features which support conditional execution and sequencing are employed in concert with a centralized-control, single-instruction, multiple data integrated video signal processor, thus adapting efficiently to the high degree of parallelism inherent in this type of video signal processing systems. A three-level prioritization scheme is used to handle the input/output data stream to improve the throughput of the processor, including provisions for distinguishing between same-priority events occurring at different times, and ensuring that in such cases the requested operations occur in the same temporal order as the respective requests.

Centralized control SIMD processor having different priority levels set

A system and method for processing data. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to gram to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.

A video processor system has memory locations for storing images including a buffer block of memory locations. Two separate video processors within the system read and write the buffer block while performing video processor functions. Each of the two video processors has its own read pointer and its own write pointer for indicating locations within the buffer block where it is currently reading or writing an image which it is processing. Both sets of read and write pointers advance through the buffer block as the images are processed. When the pointers reach the end of the buffer block they wrap around to the beginning thereby defining circular buffers. The operations of the two video processors, as well as the reading, advancing, and adjusting of the pointers, is adapted to cause the circular buffers to occupy the same physical memory locations simultaneously.

Method for controlling dataflow between a plurality of circular buffers

A data processing system having execution units for executing instruction sequences determines at least two conditionals in accordance with the instructions and sets respective flags according to the determined conditionals. These flags are stored and later retrieved sequentially and the execution unit executes selected instructions of the instruction sequence according to the sequentially retrieved mask flags. These masked flags may be stored sequentially in a stack for sequential retrieval at a later time.

Simd with selective idling of individual processors based on stored

A single-instruction multiple-data video signal processor employs a dual-ported local memory architecture in each local memory including a dedicated port for transfers between the local memory and a global memory. A block transfer controller, in combination with the dedicated port, permit each access to the global memory by a datapath processor to be overlapped with its instruction processing, thus usually avoiding stalling of the video signal processor.

Single-instruction multiple-data processor having dual-ported local

The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.

Growing community of inventors

Brooklyn, NY, United States of America

Kevin Harney