Wang Laboratories, Inc.

Kevin H Curcuru

Robert D Becker

Martin J Schwartz

Richard W Coyle

Richard F Giunta

Kenneth J Eng

A memory control unit (MCU) 22 includes a first interface for interfacing the memory control unit to one or more memory units; a second interface for interfacing the memory control unit to a system bus, including a system data bus for expressing information units, including memory read and write requests, and a system address bus. The MCU further includes logic, responsive to a write request from the system bus, for storing one or more information units within a memory unit at an address specified by the system address bus. The storing logic includes write request receiving and buffer logic having a plurality of storage locations for storing received write requests and associated write addresses prior to the execution of the write requests. The MCU further includes logic, responsive to a read request from the system bus, for reading one or more information units from a memory unit at a location specified by the system address bus. The reading logic includes read request receiving and buffer logic having a plurality of storage locations for storing received read requests and associated read addresses prior to the execution of the read requests. The memory control unit further has logic for comparing a received read address to write addresses stored in the write address buffer, the comparing logic having an output for indicating, when asserted, the occurence of the reception of a read address having a value within a predetermined range of values of one of the stored write addresses.

Memory control unit with selective execution of queued read and write

A system bus 12 for an information processing system 10 includes a first group of signal lines 16 whereon command/ID information is time multiplexed with data, and a second group of signal lines 14 for conveying address information. During a first bus cycle command/ID information is presented on the first group of signal lines while the address is presented on the second group of signal lines. During a subsequent bus cycle, and for a data write or data return operation, the first group of signal lines conveys data. Other bus connections, such as cache memories, are thus apprised of the address a full bus cycle before the data is presented thereby providing the bus connections with sufficient time to decode and otherwise operate on the bus information. Multiple word data returns from a system memory are characterized as having the address associated with a particular word of data presented in the immediately prior bus cycle, facilitating the pipelining of data and address information through the system bus. The dual functionality of the first group of signal lines eliminates the requirement for separate and dedicated command/ID and data signal line paths and associated driving and receiving circuit elements.

System bus having multiplexed command/ID and data

A system console 30 is enabled to read registers from memory boards 12 and 14 and to set registers within the memory boards which control the disabling of one or more memory arrays 16-22. The information read from the memory boards is indicative at least of which of the memory arrays has malfunctioned. The registers are within a memory logic array 40, one of which is disposed upon each of the memory boards 12 and 14 and also upon a memory controlling unit 26, the memory logic arrays being coupled together by a bit serial scan bus 42. In a preferred embodiment of the invention the memory logic arrays 40 are comprised of a highly integrated gate array semiconductor device, each of which is identical. Each memory logic array is provided with a base address input from a preceding memory logic array and computes a base address for a subsequent memory logic array. A memory logic array which has a portion of an associated memory disabled automatically determines a revised base address for the subsequent memory logic array, thereby initiating the automatic reallocation of memory board base addresses of all subsequent memory boards.

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Pepperell, MA, United States of America

Kevin H Curcuru