Xilinx, Inc.

Kevin Geary

Declan Carey

Parag Upadhyaya

Ronan Sean Casey

Mohamed N Elzeftawi

Catherine Hearne

Frantz Stephane Florent Ngankem Ngankem

Thomas Mallard

Apparatus and associated methods relate to generating a programmable differential threshold with a common mode signal derived from a received signal, and comparing a differential component of the received signal to the programmable differential threshold signal to improve signal loss detection accuracy in the presence of noise. In an illustrative example, the comparison may be performed in a signal loss detection circuit. The signal loss detection circuit may, for example, process a received input signal in an independent path in parallel with a main signal path. The programmable differential threshold may be set to a predetermined level as a function of an acceptable noise level. Based on the comparison, some implementations may advantageously respond to received signal loss, which may result from, for example, a signal path interruption.

Loss of signal detection

This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.

Continuous time linear equalization

A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

Phase interpolator and method of implementing a phase interpolator

A circuit for controlling output swing in a current-mode logic circuit is described. The circuit comprises a plurality of current-mode logic circuits coupled in series; a first current-mode logic circuit of the plurality of current-mode logic circuits coupled to provide a signal to a second current-mode logic circuit of the plurality of current-mode logic circuits; an amplitude detector coupled to detect an amplitude of the signal received at the second current-mode logic circuit; and a control circuit coupled to the amplitude detector; wherein the control circuit generates an amplitude control signal for a current-mode logic circuit of the plurality of current-mode logic circuits based upon a detected amplitude of the signal received at the second current-mode logic circuit. A method of controlling output swing in a current-mode logic circuit is also disclosed.

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Ballincollig, Ireland

Kevin Geary