International Business Machines Corporation

Kevin G Kramer

Gene J Gaudenzi

Louis L Hsu

Michael Anthony Sorna

Jonathan Mark Haswell

James D Rockrohr

Robert Michael Bunce

Huihao Xu

Susan L Tempest

Daryl Carvis Cromer

Christos J Georgiou

Mark Edward Dean

Patrick M Bland

William Richard Kelly

Brian Joel Schuh

Louis T Fasano

Timothy J Louie

Paul C King

Dinesh B Nair

A design structure embodied in a machine-readable medium used in a design process may include a system for detecting a fault in a signal transmission path. Such system may include, for example, a hysteresis comparator including a latch having n-type field effect transistor ('NFET') storage elements. The hysteresis comparator may be operable to detect a crossing of a reference voltage level by an input signal arriving from the signal transmission path such that when the comparator does not detect an expected crossing of the reference voltage level by the input signal, the fault is determined to be detected in the signal transmission path.

Structure for robust cable connectivity test receiver for high-speed data receiver

A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.

Robust cable connectivity test receiver for high-speed data receiver

A method for on-chip detection of data lock and measurement of data lock time in a high-speed serial data link, including: permitting one or more incoming data streams into the high-speed data link; establishing a pattern to be searched in the one or more incoming data streams; comparing patterns in the one or more incoming data streams to a programmable data pattern; holding a repetitive pattern of bits in the one or more incoming data streams by one or more programmable data pattern registers, wherein when one or more occurrences of a byte are detected, an appropriate bit in the one or more programmable data pattern registers is set to indicate the byte's relative position; and filtering false indications in the repetitive pattern by using a byte detection state machine, the state machine controlling and keeping track of a search progress.

On-chip detection and measurement of data lock in a high-speed serial data link

A method of detecting error during transfer of instructions from a data memory to a computer processor. At the time of the commencement of transmission of the instructions, the raw data signal is checked for an error detection code indicating data corruption. If the error detection code indicates no data corruption, the transmission of the instruction to the computer processor is completed. However, if data corruption is indicated, the raw data signal is substituted with a predetermined reserved signal or instruction and transmitted to the computer processor. An attempt is made to correct the corrupted data in the raw data signal and, if it is corrected, the corrected data signal is subsequently retrieved and the corrected data signal is processed by the computer processor. The corrupted raw data signal in the data memory may be replaced with the corrected data signal.

Method and system for optimized instruction fetch to protect against soft and hard errors

A data communication controller processes incoming data frames. The controller includes a pre-processing block for receiving data frames and a frame processing unit coupled to the pre-processing block. The pre-processing block is configured to compare header fields of a current frame with header fields of a previous frame. The pre-processing block provides an output signal to the frame processing unit on the basis of the comparison of the header fields of the current and previous frames. The controller may operate in accordance with the Fiber Channel protocol, and the output signal may include bits to indicate that the current frame is of the same exchange, of the same sequence, and is next in sequence relative to the previous frame.

Inbound data stream controller with pre-recognition of frame sequence

An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.

ECC function with self-contained high performance partial write or

A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

Bidirectional buffer with latch and parity capability

A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

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Wappingers Falls, NY, United States of America

Kevin G Kramer