International Business Machines Corporation

Kevin Franklin Reick

Michael Stephen Floyd

James Stephen Fields, Jr

Larry Scott Leitner

Timothy Michael Skergan

Guy L Guthrie

Paul Frank Lecocq

Brian Chan Monwai

Ravi Kumar Arimilli

James Allan Kahle

Alexander Erik Mericas

Thomas Pflueger

Scott Barnett Swaney

Hung Qui Le

David Dean Sanner

Joel Roger Davidson

Harmony Lynn Helterhoff

Jennifer Lane Vargus

Michael Steven Siegel

Hugh Shen

Frank David Ferraiolo

Bartholomew Blaner

Kenneth Lee Wright

Phillip G Williams

Robert Alan Cargnoni

Alongkorn Kitamorn

Samuel I Ward

Thomas Edward Rosser

Jeff A Stuecheli

Bradley David McCredie

Bryan J Robbins

Nathaniel R Chadwick

Jon Robert Tetzloff

Robert J Shadowen

James M Crafts

Jeffrey W Kellington

Joel M Tendler

Allen R Hall

Bjorn P Christensen

Judith K Laurens

Derek E Williams

Daniel Mark Dreps

Lakshminarayana Baba Arimilli

Paul Joseph Jordan

Lee Evan Eisen

David James Shippy

Robert J Reese

David Otto Lewis

Edward John Silha

Larry Edward Thatcher

Christopher John Engel

Norman Karl James

John Edward Derrick

Philip George Shephard, Iii

Michael Youhour Lim

Daniel Morgan Crowell

Carl J Anderson

Roger Ned Bailey

Thi Ngoc Tran

Keenan Wynn Franz

Ryan Joseph Pennington

Wayne L Lemmon

John Anthony Moore

Judith E K Laurens

Kevin Dennis Woodling

Hugh Rodney Stigdon

John David Purcell

Harmony L Prince

Michael Stephen Floys

Marco Zamora

A method for facilitating adaptive frequency in a processor having a plurality of cores. The method can include conducting tests on the processor; determining, via the processor testing system, default parameters for operating one or more of the cores, wherein the default parameters are based on results of the tests and cause one or more of the cores to operate within production yield goals of the processor; determining alternative parameters for operating one or more of the cores, wherein the alternative parameters are based on results of the test and cause one or more of the cores to operate outside production yield goals of the processor, and wherein the alternative parameters are usable to reconfigure one or more of the cores after an initial operation per the default parameters; and writing the default parameters and the alternative parameters to a production data storage of the processor.

Adaptive frequency optimization in processors

A processor can have a plurality of cores. A first core processor of a first core can read one or more values of a default parameter set. The first core can be operated in accordance with a first operating characteristic based, at least in part, on the one or more values of the default parameter set. The first core processor can receive an indication to change the operating characteristic of the first core processor. In response to receiving the indication to change the operating characteristic, a signal can be issued to the first core processor to reset. In response to the reset, the first core processor can read one or more values of an alternative parameter set. The first core processor can then be operated in accordance with a second operating characteristic based, at least in part, on the one or more values of the alternative parameter set.

A method provides processor initialization in different platform environments via a single code set. The method includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The method further includes performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated. The HWP framework includes standard interfaces and enables direct updates to hardware procedures without requiring a new flash code or a firmware patch.

Data driven hardware chips initialization via hardware procedure framework

A system and computer program product provide processor initialization in different platform environments via a single code set. The system includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The system further includes the microcontroller performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated. The HWP framework includes standard interfaces and enables direct updates to hardware procedures without requiring a new flash code or a firmware patch.

A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP includes an epoch timer that advances at regular intervals to define epochs of operation of the CAPP. Each of one or more entries in a data structure in the CAPP are associated with a respective epoch. Recovery operations for the CAPP are initiated based on a comparison of an epoch indicated by the epoch timer and the epoch associated with one of the one or more entries in the data structure.

Epoch-based recovery for coherent attached processor proxy

A method, system, and computer program product for changing hardware in a data processing system without disrupting processes executing on the data processing system. A hardware change to a selected portion of hardware in the data processing system may be required, such as to repair hardware errors or to implement a system update. Responsive to a determination that a hardware change to the selected portion of the hardware is required, a process being performed by the selected portion is moved from the selected portion of the hardware to an alternate portion of the hardware. The hardware change is applied to the selected portion of the hardware. The selected portion of the hardware is returned for use by the data processing system after the hardware change is applied.

Non-disruptive hardware change

A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks. The second behavioral model and the configuration file are together configured for input to a synthesis tool.

Circuit design optimization

A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure. In the event the first logic structure causes a coverage problem, the testability model is modified to include an inversion structure. The inversion structure is configured based on the first logic structure. The inversion structure is configured to generate an inversion structure output. The testability model is modified to couple the inversion structure output as an input to the error circuit.

A processing unit includes a processor core and a cache memory coupled to the processor core. The cache memory includes a data array, a directory of the data array, error detection logic that sequentially detects a first, second and third correctable errors in the data array of the cache memory and provides indications of detection of the first, second and third correctable errors, and control circuitry that, responsive to the indication of the third correctable error and an indication that the first and second correctable errors occurred at too high a frequency, marks an entry of the data array containing a cache line having the third correctable error as deleted in the directory of the cache memory regardless of which entry of the data array contains a cache line having the second correctable error.

Delete of cache line with correctable error

In response to a data request of a first processing unit among a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and selects the lower level cache of a second of the plurality of processing units as an intended destination of a lateral castout (LCO) command by randomized round-robin selection. The first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and the intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held in the lower level cache of one of the plurality of processing units other than the first processing unit.

Lateral castout target selection

In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Apparatus for operating cache-inhibited memory mapped commands to access registers

A mechanism is provided for recovering from a data scan error. A service processor determines the nature of the data scan error and, depending on the nature of the error, performs one of a plurality of data scan error recovery procedures.

Recovery from hardware access errors

Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.

Providing low-level hardware access to in-band and out-of-band firmware

A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor

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Round Rock, TX, United States of America

Kevin Franklin Reick