Intel Corporation

Wisconsin Alumni Research Foundation

Kevin Fischer

Vinay B Chikarmane

Brennan Peterson

Peter K Moon

Jun He

Ying Zhou

Michael A Childs

Abhishek A Sharma

Mauro J Kobrinsky

Wilfred Gomes

Ruth Amy Brain

Andrew W Yeoh

Tahir Ghani

Biswajeet Guha

Brian Joseph Greene

Bernhard Sell

Curtis Tsai

Chung-Hsun Lin

Christopher M Pelto

Conor P Puls

Rishabh Mehandru

Sanka Ganesan

Gregory F Taylor

Yogesh B Gianchandani

William Hsu

Sanjay S Natarajan

Henry Guckel

Doug B Ingerly

Mohamed A Abdelmoneum

Tawfik M Rahal-Arabi

Ayan Kar

Kalyan C Kolluru

Nicholas A Thomson

Avyaya Jayanthinarasimham

Nathan Jack

Rui Ma

Benjamin Orr

Qiang Fu

Daniel Schulman

Lin Hu

Sabih Omar

Pavel S Plekhanov

Hiroki Hiramatsu

Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Substrate-free integrated circuit structures

Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

Integrated circuit assemblies with direct chip attach to circuit boards

Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

Substrate-less electrostatic discharge (ESD) integrated circuit structures

Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

Thin film transistor based memory cells on both sides of a layer of logic devices

A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

AVD hardmask for damascene patterning

An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

Thickened stress relief and power distribution layer

Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

Interconnects having sealing structures to enable selective metal capping layers

An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.

On-chip capacitors and methods of assembling same

A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having at least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

An airgap interconnect structure with hood layer and methods for forming such an airgap interconnect structure are disclosed. A substrate having a dielectric layer with a plurality of interconnects formed therein is provided. Each interconnect is encapsulated by a barrier layer. A hardmask is formed on the dielectric layer and patterned to expose the dielectric layer between adjacent interconnects where an airgap is desired. The dielectric layer is etched to form a trench, wherein the etching process additionally etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect. A hood layer is electrolessly plated onto an exposed portion of the top surface and the exposed portion of the side surface to reseal the interconnect. A gap-sealing dielectric layer is formed over the device, sealing the trench to form an airgap.

Airgap interconnect with hood layer and method of forming

Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (E) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (V); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material. In some instances, such a layer may serve as an etch stop.

Techniques for enhancing dielectric breakdown performance

Growing community of inventors

Hillsboro, OR, United States of America

Kevin Fischer