Unisys Corporation

Other

Kevin F Jennings

Robert D Klein

George E Reasoner, Jr

Gerald R Smith

David C Williams

Debora Y Grosse

Robert D'Aoust

Stephen R Krebs

Robert B Cording

Audrey A Brennan

Arnold Marshall

A parabolic trough solar collector system has a parabolic reflector used with an independently supported collector tube. The parabolic reflector has a reflective surface formed on a reflective surface support structure, supported by a circular support beam. This assembly rests on a plurality of support and drive rollers supported by a roller support arm, supported by a roller support column. The parabolic reflector assembly rotates against the rollers along a single axis to maintain a focus line of the parabolic reflector surface at the same location as the center of the circle described by the outer edge of the circular support beam. Located at this same focus line is the independently supported collector tube not attached to the parabolic trough reflector. The collector tube is supported on pipe roller hangers, which in turn are supported by a wire catenary system connected to support towers which straddle the parabolic reflector.

Parabolic trough solar reflector with an independently supported collector tube

A serial load controller and method for loading at least one input data bit serially into a memory. The memory is interfaced to a data bus and an address bus. The serial load controller includes a counter generating an internal address pointer signal in response to a first control signal. The first control signal indicates that the input data bit is to be transferred serially into the memory. The counter is responsive to the first control signal to reset the internal address pointer to an initial value. A multiplexer is coupled to select one of the address bus and the internal address pointer signal as an output address bus in response to the first control signal. Suitable transceivers or other bus drivers are provided for driving at least a first input data bit onto the data bus in response to the clock pulse.

Serially loadable digital electronic memory and method of loading the same

A method for controlling a high speed memory unit M to be read from, and written to, as initiated by clock signals of comparable speed, this method involving: providing a timing coordinator unit with bi-stable store for storing and presenting certain input signals to the memory unit in conjunction with the clock signals so as to be immediately useable thereby and so that the memory unit can responsively output data to a user stage; these input signals being arranged to include commands R/W to Read or Write, Address signals and Data signals; and the memory unit being maintained in &ldquo;ready-to-read&rdquo; condition at all times except during receipt of write commands.

Method for controlling high speed digital electronic memory

The invention includes apparatus for controlling a high speed memory unit M that is written to on every cycle and read from on every cycle except during receipt of write commands. The apparatus includes a timing coordinator with bi-stable storage means that store and present certain signals to the memory in conjunction with clock signals so as to be immediately usable by the memory, and so that the memory can responsively output data to a user. The signals include commands R/W to Read or Write, Address signals and Data signals.

High speed digital electronic memory having a read and write in one cycle

Protective cap for shelving upright

An apparatus for and method of granting access to a shared resource wherein the shared resource is accessed by a plurality of users. In a first exemplary embodiment of the present invention, a priority controller can assign priority to a number of users based upon the combination of shared resource request signals received by the priority controller. For each combination of shared resource request signals, a different priority may be assigned to each user by the priority controller. In another exemplary embodiment of the present invention, each user may supply additional information bits to the priority controller to indicate a 'requested priority' for a the shared resource. The priority controller then weighs the priority requests from each user, including the additional information bits, and determines an optimum priority assignment. That is, the users themselves may influence the priority assigned thereto by providing the additional information bits to the priority controller.

Method and apparatus for high-speed efficient bi-directional

An apparatus for and method of providing a system whereby a number of processors may communicate with a memory device and wherein the memory device may operate at a slower speed without substantially reducing the band pass of the computer system. Further, one or more of the processors may have a different data word width from the other processors and from the memory device. The present invention may minimize the amount of wasted memory bits contained therein by concatenating data words such that the resulting data word substantially matches the word width of the memory device. The present invention further allows predefined portions of a data word to be placed in an order and concatenated with predefined portions of the same data word or with predefined portions of other data words. A number of predetermined formats define the selection and the order that the predefined portions may be placed. Various formats are contemplated and are described herein.

Method and apparatus for efficiently interfacing variable width data

An image processing hardware element that may be used to implement any number of data manipulation methods. The hardware element may be dedicated to the selected manipulation method such that maximum performance may be attained. The hardware element may be programmed to implement a particular manipulation method by simply down loading new values into the hardware element.

Method and apparatus for high-speed implementation of scaling,

An application specific integrated circuit (ASIC) provides sufficient information about the size of the image, as well as pixel data, to permit a scaling processor to change the size of the image for further processing.

Method and apparatus for scaling image data

A pipelined image processor is disclosed which contains a diagnostic apparatus which, under normal processing conditions, is coupled to and is in communication with resequencer, image processor, and transposer/compressor assemblies contained within the pipelined image processor. The diagnostic apparatus of this invention causes a diagnostic test pattern to be sent to the re-sequencer and image processor entities of the pipelined image processor and monitors the response thereof. This response is then used to detect faults which have occurred in these entities.

Growing community of inventors

Novi, MI, United States of America

Kevin F Jennings