International Business Machines Corporation

Lattice Semiconductor Corporation

Lucent Technologies Inc.

Kevin E Sallese

Timothy J Fisher

Charles John Camp

Aaron Daniel Fry

Adalberto Guillermo Yanes

Nikolaos Papandreou

Jason Szecheong Ma

Charles A Keller

Van Huynh

Roman Alexander Pletka

Lincoln T Simmons

David A Pierce

Thomas A Peterson

Shu Yuan

Ashwitha Krishna Kumar

Charalampos Pozidis

Andrew Dale Walls

Nikolas Ioannou

Sasa Tomic

Robert Edward Galbraith

Christopher M Dennett

Cyril Varkey

Frank Manuel Reveles

Charles Joseph Wilde

Provided are a method, an apparatus, and a memory controller coupled to a plurality of storage dies, wherein the memory controller implements logic to perform operations with respect to the storage dies, the operations comprising: maintaining a calendar based scheduling mechanism that is programmed by a firmware to support a quality of service scheduling in a solid state drive in which the memory controller is included; and determining, by a flash command scheduler, from the calendar based scheduling mechanism, which traffic class to service.

Calendar based flash command scheduler for dynamic quality of service scheduling and bandwidth allocations

Provided are a memory controller, system, and method for generating multi-plane reads to read pages on planes of a storage die for a page to read. A memory controller determines planes for a read to a page. A storage die of the storage dies includes a plurality of planes having a plurality of blocks and the blocks have pages. The page to read is implemented in pages on the planes. The memory controller determines threshold voltages for the pages in the determined planes and determines a derived threshold voltage from the determined threshold voltages. The derived threshold voltage is used to perform multi-plane reads of the pages from the determined planes.

Generating multi-plane reads to read pages on planes of a storage die for a page to read

A computer-implemented method, according to one embodiment, includes: receiving a sub-logical page read command for data stored in NVRAM at a first LBA, and creating a searchable entry which includes the first LBA. Data read from the NVRAM is also received, where the received data corresponds to a given LBA. In response to determining that the given LBA matches the first LBA of the searchable entry, a copy of the received data is stored in a buffer. Moreover, in response to determining that a received sub-logical page write command is for data stored in the NVRAM at the first LBA, the copy of the received data in the buffer is coalesced with data included in the sub-logical page write command to form a full-logical page write. Furthermore, instructions to perform the full-logical page write in the NVRAM are sent.

Performing sub-logical page write operations in non-volatile random access memory (NVRAM) using pre-populated read-modify-write (RMW) buffers

A computer-implemented method, according to one embodiment, includes: receiving a stream of data, and selecting more than one block of memory to write the stream of data to. The selected blocks of memory are in a memory that includes a plurality of blocks. Moreover, the data is written across the selected blocks of memory in parallel. The blocks of memory are also selected such that no two or more of the selected blocks of memory have an effect on a read apparent voltage of a same one of the plurality of blocks in the memory. Other systems, methods, and computer program products are described in additional embodiments.

Reducing effects of read array operations of read apparent voltage

A computer-implemented method, according to one embodiment, includes: receiving a multi-page read request and predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range. In response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, a threshold voltage shift (TVS) value is computed for the multi-plane read operation. Furthermore, the pages are read using the multi-plane read operation with the computed TVS. Other systems, methods, and computer program products are described in additional embodiments.

Selectively performing multi-plane read operations in non-volatile memory

A computer-implemented method, according to one embodiment, includes: receiving a data access command which corresponds to data stored on NVRAM at a logical block address, and using content-addressable memory (CAM) to determine whether the logical block address corresponds to an active read modify write operation. In response to determining that the logical block address corresponds to an active read modify write operation, the data access command is satisfied using a first procedure. However, in response to determining that the logical block address does not correspond to an active read modify write operation, the data access command is satisfied using a second procedure. Moreover, using the CAM to determine whether the logical block address corresponds to an active read modify write operation is completed in a single clock cycle of the CAM.

Using content addressable memory to perform read-modify-write operations in non-volatile random access memory (NVRAM)

Read Apparent Voltage (RAV) is an anomality in which an apparent threshold voltage of a storage cell transistor does not equal the actual threshold voltage of that same transistor by a large enough magnitude that the binary state of transistor is not read correctly. An infector page may cause the RAV anomality within a different infected page. To determine whether any page is an infector, each page is programmed, a page within each block is read, an acting infector page within an acting infector block is set, a possible infected page within a possible infected block is set, the acting infector page is read a predetermined plurality of instances, the possible infected page is read, a raw bit error rate (RBER) of the read of the possible infected page is determined, and the acting infector page is set as an actual infector page based upon the determined RBER.

Determining a read apparent voltage infector page and infected page

Technology for handling page size mismatches when DPL-CLR is performed at multiple levels of a data storage system (for example, RAID level and flash card level). A 'corrective DPL' corrects only a portion of the data that would make up a page at the level at which the data is stored (that is, the 'initial DPL level'), and, after that, a partially corrected page of data is formed and stored in data storage, with the partially corrected page: (i) having a page size characteristic of the initial DPL; (ii) including the part of the data corrected by the corrective DPL; and (iii) further including other data. In some embodiments, the other data has a pattern that indicates that it is invalid, erroneous data, such that an error message will be returned if this portion of the data is attempted to be read.

Corrupt logical block addressing recovery scheme

A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.

Reducing read errors by performing mitigation reads to blocks of non-volatile memory

A storage system includes a controller connected to a solid state memory device. The controller releases the physical address for reassignment when no pending reads are associated with the physical address. In certain embodiments, a read status table may be included within the storage system. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Physical address management in solid state memory by tracking pending reads therefrom

According to one embodiment, a method includes issuing a read request to read one or more units of data from at least one non-volatile random access memory (NVRAM) device. The read request includes one or more read voltage thresholds. The method also includes receiving the one or more data units and read command parameters used to read the one or more data units from the at least one NVRAM device. Moreover, the method includes storing error-free data units, the read command parameters used to read the error-free data units from the at least one NVRAM device, and a read completion status to one of a plurality of read buffers. The read completion status indicates a completed read when a data unit is error-free and indicates an incomplete read when a data unit is errored.

Read buffer architecture supporting integrated XOR-reconstructed and read-retry for non-volatile random access memory (NVRAM) systems

A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Physical address management in solid state memory

According to one embodiment, a system includes a read buffer memory configured to store data to support integrated XOR reconstructed data and read-retry data and logic configured to receive data units and read command parameters used to read the data units from a non-volatile random access memory (NVRAM) device, determine which read buffers from the read buffer memory to store the data units, determine an error status for each of the data units, wherein the error status indicates whether each data unit includes errored data or error-free data, store each error-free data unit and the read command parameters to a corresponding read buffer, reject each errored data unit without affecting a corresponding read buffer, and retry to read only errored data units from the NVRAM device until each of the data units is stored in the read buffer memory.

Growing community of inventors

Plainfield, IL, United States of America

Kevin E Sallese