National Semiconductor Corporation

Foveon, Inc.

Foveonics, Inc.

Exar Corporation

Kevin E Brehmer

Richard B Merrill

Ha Chu Vu

Douglas Robert Farrenkopf

Philip J Cacharelis

Kamesh V Gadepally

Ion E Opris

James B Wieser

Carlos A Laber

Wieser James B

An active pixel sensor cell array in which a two-stage amplifier amplifies the output of each cell. The two-stage amplifier design reduces fixed pattern noise in the image data generated by reading the array, by providing increased gain for the output of each cell without impractically increasing the size and complexity of each cell. For each column of cells of the array, one part of the two-stage amplifier for each cell is shared by all cells of the column, and another part of the two-stage amplifier for each cell is included within the cell itself. Preferably, each cell includes only NMOS transistors (no cell includes a PMOS transistor). In preferred embodiments, a differential amplifier within each cell is the primary stage of the cell's output amplifier, PMOS load circuitry including a secondary output amplifier stage is shared by all cells of the column, and the two amplifier stages for each cell together comprise an op amp. In some such preferred embodiments, the op amp is provided with capacitor feedback for increased gain. Another aspect of the invention is an active pixel sensor cell including a differential amplifier, and PMOS transistor load circuitry coupled to the cell. Preferably, the differential amplifier is the first stage of an op amp, and the remainder of the op amp, including optional capacitor feedback circuitry, is coupled to the cell but is not included within the cell.

Two-stage amplifier for active pixel sensor cell array for reducing fixed pattern noise in the array output

The blue signal of a CMOS-based color pixel is increased with respect to the red and green signals by lowering the doping concentration of the surface regions of the pn-junction photodiodes that are used in the blue imaging cells with respect to the surface regions of the pn-junction photodiodes that are used in the red and green imaging cells.

CMOS-based color pixel with reduced noise in the blue signal

An analog signal sampler with improved correlated double sampling (CDS) performance for imaging systems includes a dual mode input amplifier, a switched capacitor network and a differential amplifier. The dual mode input amplifier has a high input impedance and allows for receiving either positive-going contact image sensor (CIS) or negative-going charge couple device (CCD) image signals as desired. The switched capacitor network and differential amplifier together perform an improved CDS of the image signal and convert the unipolar input image signal to a bipolar differential output signal with an improved dynamic signal range. The CDS technique used relies upon simultaneous charging of the coupling and sample and hold capacitances with charge transfer from the coupling capacitance to the sample and hold capacitance. The gain of the sampler can be programmed by appropriate selection of the ratio of the coupling capacitance to the sample and hold capacitance.

Analog signal sampler for imaging systems

The noise in the photo information extracted from an active pixel sensor cell is reduced by resetting the voltage on the photodiode of the cell to the power supply voltage, and by reading the cell immediately before and after the cell is reset. The voltage on the photodiode is reset to the power supply voltage by applying a reset voltage to the gate of the reset transistor conventionally used to reset the photodiode where the reset voltage is sufficiently larger than the power supply voltage to cause the voltage on the photodiode to be pulled up to the power supply voltage.

Method for operating an active pixel sensor cell that reduces noise in

An active pixel sensor cell array in which a differential amplifier (whose output is fed back to one of its inputs) amplifies the output of each cell. By using such differential amplifiers, fixed pattern noise in the image data generated by reading the array is reduced. Part of the differential amplifier for each cell is within the cell itself and a current source and tail current sink for the differential amplifier are implemented outside the cell and shared by all cells connected along a column of the array. Preferably, the output amplifier circuitry within each cell includes no PMOS transistor (although it typically includes NMOS transistors). Another aspect of the invention is an active pixel sensor cell including part of a differential amplifier (having an output fed back to one of its inputs, and configured to assert an amplified signal indicative of a sampled output voltage of the cell's photodiode), and circuitry (physically separate from the cell) implementing a remaining portion (e.g., a current source and tail current sink) of the differential amplifier.

Active pixel sensor cell with differential amplifier and array including

Two-stage amplifier for active pixel sensor cell array for reducing

Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

Fabrication of semiconductor structure having two levels of buried

Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricatable from a semiconductor structure having two levels of buried regions. In a typical embodiment lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. Upper buried regions of opposite conductivity type are similarly situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is normally configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

Semiconductor structure having two levels of buried regions

A MOSFET amplifier includes an amplifier stage with a boosted transconductance and a differential current mirror. The amplifier stage with a boosted transconductance includes complementary MOSFETs cross-connected with a fixed current source whereby the drain-to-source current and, therefore, the gate-to-source voltage, of the input MOSFET is fixed by the current source, while the drain-to-source current of the other MOSFET is dependent upon the input signal voltage. The differential current mirror includes a multiple branch differential input stage with a bridging resistor connected between the differential branches. The bridging resistor conducts a bridging current which equals one half of the difference between the differential branch currents, is substantially zero when the differential input voltage is zero and is nonzero when the differential input voltage is nonzero. Variable voltage gain is provided by a serial arrangement of voltage-to-current and current-to-voltage converters with a controllable current gain.

High speed variable gain amplifier

A multistage pipelined analog to digital converter architecture that significantly reduces non-linearity by a novel control switching technique is introduced. A first aspect of the present invention embraces a sample and hold circuit that includes a logic circuit, a plurality of reference signal nodes, an input signal node, an output signal node, a sample signal node, a first switching node, a second switching node, a circuit reference node, a first capacitor, a second capacitor, a signal routing circuit, and amplifier, which are inter-coupled to provide an output analog residue signal. At each stage of the pipelined architecture the sample and hold switch control logic alternately samples and amplifies signals inputted thereto and effectively reduce capacitor mismatch errors. This has the advantageous result of reducing non-linearity. According to a second aspect, the sample and hold circuit uses a differential amplifier having an inverting input and a non-inverting input. This second aspect further employs sequential termination of the amplifying time period resulting in additional advantage of reducing charge injection.

Pipeline analog to digital converter architecture with reduced mismatch

A programmable delay for the gate signal output of the differentiator in a data analyzing circuit is provided. A data signal is produced by a low pass filter, and a differentiator (high pass filter) produces a gate signal. The cutoff frequency of the low pass filter is controlled by a first control circuit, and a second control circuit is provided to separately control the cutoff frequency of the high pass filter. The second control circuit produces a variation from the base frequency determined by the first control circuit. Thus, the cutoff frequency of the high pass filter will always be proportional to that of the low pass filter.

Programmable differentiator delay

A CMOS high gain strobed comparator comprising a cascoded input differential stage with current mirror loads. The DC biasing for the input stage cascode devices is set by a replica biasing technique. The loads to the input differential stage are simple current mirrors which drive a set of cross-coupled devices that form a latch. The high gain of the comparator is realized in the second stage. The differential output of the comparator drives a second latch. This second cross-coupled latch stores and maintains the comparator data even after the strobe signal destroys the data of the differential output.

High input impedance, high gain CMOS strobed comparator

A CMOS Class AB power amplifier is disclosed wherein supply-to-supply voltage swings across low resistive loads are efficiently and readily handled. A high gain input stage including a differential amplifier driving a common source amplifier drives unity gain push-pull output stage. Included in the invention is circuitry to control the DC bias current in the output driver devices in the event of an offset between the push-pull unity gain amplifiers.

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San Jose, CA, United States of America

Kevin E Brehmer