Eliyan Corporation

Kevin Donnelly

Ramin Farjadrad

Syrus Ziai

Curtis McAllister

An integrated circuit (IC) chip includes a Universal Chiplet Interconnect express (UCIe) interface circuit for transferring UCIe signals. The UCIe interface circuit includes a mainband sub-interface for transferring mainband signals and a sideband sub-interface for transferring sideband signals along a first number of sideband signal paths. A bump interface includes a second number of sideband bumps, each of the sideband bumps for coupling to a signal link. The second number of sideband bumps is less than the first number of sideband signal paths. A converter circuit is disposed between the UCIe interface circuit and the bump interface. The converter circuit includes a receiver circuit to receive first sideband data from the sideband sub-interface. The receiver circuit includes local clock circuitry, oversampling circuitry, and majority detection circuitry to receive oversampled data and to resolve states of sideband data bits based on a majority voting process.

Interface conversion circuitry for universal chiplet interconnect express (UCIe)

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes a D2D interface of a first type for coupling to a host IC chip via multiple lanes. The D2D interface includes multiple unit interface modules, each of the multiple unit interface modules corresponding to a first set of signal path resources of a lowest granularity provided by the multiple lanes. A memory port includes a memory physical interface of a first memory type for accessing memory storage of the first memory type. The memory physical interface of the first memory type includes a second set of signal path resources corresponding to multiple memory channels of the first memory type. Mapping circuitry maps the second set of signal path resources to the first set of signal path resources in a manner that utilizes all of the first signal path resources for an integer number of the multiple unit interface modules.

Memory chiplet with efficient mapping of memory-centric interface to die-to-die (D2D) unit interface modules

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and an integrated circuit (IC) processor chip disposed on the package substrate. The IC processor chip includes a data interface configured to support N channels. A scalable high bandwidth memory (HBM) is coupled to the IC processor chip. The scalable HBM includes a first HBM device disposed on the package substrate with a first primary data interface that supports a first set of N/2 data channels and a first data transfer rate. A second HBM device is disposed on the package substrate and supports a second set of N/2 data channels and a second data transfer rate. The first HBM device and the second HBM device are configured to collectively support the full N channels and an aggregate data rate that is a sum of the first data rate and the second data rate.

Growing community of inventors

Santa Cruz, CA, United States of America

Kevin Donnelly