Intel Corporation

Kevin Dai

Stephen H Gunther

Robert J Greiner

Matthew M Ma

Alon Naveh

Keng L Wong

Terry I Chappell

Roman Surgutchik

Hung-Piao Ma

The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Dynamic voltage transitions

In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.

Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device

A method and apparatus provides an efficient ratioed digital logic structure. The digital logic structure includes ratioed pull-up transistors and pull-down transistors such that the circuit noise margin does not substantially affect gain performance of the ratio stage. In one particular embodiment, a ratioed logic structure includes PMOS transistors and NMOS transistors that receive input voltage signals wherein a current path is induced in the NMOS transistors when a voltage input of zero or less is applied. Another feature of the present invention allows modification of gain performance of the ratio stage by arranging different ratios of the PMOS-to-NMOS transistor channel widths.

Method and apparatus for ratioed logic structure that uses zero or negative threshold voltage

An embodiment of the present invention includes a switchable conductive pathway between a number of intermediate nodes in a domino stage, up to and including every intermediate node, and a voltage source. In operation, this circuit configuration prevents the problems associated with charge sharing. The voltage, at the voltage source which is coupled to the intermediate nodes, is substantially equal to the voltage at a voltage source that is coupled by way of a domino precharge circuit to the output node of the domino stage. The switchable conductive pathways are switched on at the start of the precharge phase, and switched off at the beginning of the evaluation phase. In this way, intermediate node voltages in a domino stage are actively maintained, even after the main precharge control signal has been deasserted. Active maintenance of the intermediate nodes is suspended during the evaluation phase. In a further aspect of the present invention, the switchable conductive pathways in the domino stages of a first domino chain are controlled by signals that are generated by a second domino chain that is parallel to the first domino chain.

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San Jose, CA, United States of America

Kevin Dai