United States of America As Represented by the Secretary of the Air Force

Kevin D Leedy

John L Ebel

Richard E Strawser

Rebecca Cortez

Burhan Bayraktaroglu

Donald E Strawser, Legal Representative

Robert L Crane

Ronald A Coutu, Jr

Gregg H Jessen

Paul E Kladitis

Andrew J Green

Michael L Schuette

Robert C Fitch, Jr

A monolithically integrated circuit comprising a semiconducting wafer, a metal oxide thin film semiconductor device disposed adjacent a first region of the semiconducting wafer, and a dissimilar semiconductor device disposed adjacent a second region of the semiconducting wafer and fabrication methods thereof.

Metal oxide thin film semiconductor device monolithically integrated with dissimilar device on the same wafer

A method of fabricating a multi-zone, short gate length thin film transistor is provided. Gate metal and a plurality of layers are deposited on a substrate. The layers include a gate insulator, a first semiconductor, a second semiconductor, and source contact metal. An insulator is deposited on the plurality of layers partially overlapping the gate electrode and masking part of the plurality of layers. Portions of the source contact metal not masked by the insulator are removed and the first and second semiconductors are diffused with dopants via a plasma. Sidewalls of the insulator and source metal contact are covered with an insulating layer. Portions of the second semiconductor not masked are removed by etching for a length of time to create undercuts below the insulator and extending under the source contact metal. The undercuts are filled with an insulating material and an external metal contact layer is deposited.

Fabrication method for multi-zoned and short channel thin film transistors

A method is provided for fabricating a thin film transistor. An insulating and a metal gate contact layer are deposited on a substrate with the insulating layer being positioned between the gate contact layer and the substrate. A portion of the gate contact layer is selectively removed utilizing reactive ion etching incorporating a gas that etches the gate contact layer but not the insulating layer. A plurality of layers is deposited over a remaining portion of the gate contact layer and insulating layer, which include a gate insulating layer, a channel layer, and a metal film. A portion of the metal film is selectively removed utilizing reactive ion etching incorporating the gas that etches the metal film but not the channel layer. The insulating layer includes a high resistivity insulator that can be deposited at temperatures less than 400&#xb0; C. and the channel layer is comprised of a metal oxide semiconductor.

Metal oxide thin film transistor fabrication method

A method is provided for fabricating a thin film transistor. A plurality of layers is deposited on a substrate. The plurality of layers includes a conductive gate contact layer, a gate insulator layer, an undoped channel layer, an etch-stop layer, and a conductive contact layer. The etch-stop layer is positioned between the conductive contact layer and the undoped channel layer. A portion of the conductive contact layer is selectively removed while removal of a portion of the undoped channel layer is prevented by the etch-stop layer during the selective removal. A portion of the etch-stop layer is selectively removed and an exposed portion of the etch-stop layer is converted from a conductor to an insulator by oxidizing the exposed portion of the etch-stop layer in air. A portion of remaining layers of the plurality of layers is selectively removed to form the thin film transistor.

Fabrication method for ZnO thin film transistors using etch-stop layer

A process for making a latching zip-mode actuated mono wafer MEMS switch especially suited to capacitance coupled signal switching of microwave radio frequency signals is disclosed. The single wafer fabrication process used for the switch employs sacrificial layers and liquid removal of these layers in order to also provide needed permanent physical protection for an ultra fragile switch moving arm member. Latched operation of the achieved MEMS switch without use of conventional holding electrodes or magnetic fields is also achieved. Fabrication of a single MEMS switch is disclosed however large or small arrays may be achieved. A liquid removal based fabrication process is disclosed.

Latching zip-mode actuated mono wafer MEMS switch method

A latching zip-mode actuated mono wafer MEMS switch especially suited to capacitance coupled signal switching of microwave radio frequency signals is disclosed. The single wafer fabrication process used for the switch employs sacrificial layers and liquid removal of these layers in order to also provide needed permanent physical protection for an ultra fragile switch moving arm member. Latched operation of the achieved MEMS switch without use of conventional holding electrodes or magnetic fields is also achieved. Fabrication of a single MEMS switch is disclosed however large or small arrays may be achieved.

Latching zip-mode actuated mono wafer MEMS switch

A digital variable capacitor package is provided as having a ground plane disposed on predetermined portion of the top surface of a substrate. An elongated signal electrode may also be disposed on the substrate and including a first end defining an input and a second end extending to a substantially central region of the top surface of the substrate. This elongated signal electrode is disposed to be electrically isolated from the ground plane. A number of elongated cantilevers are disposed on the substrate and each include first ends coupled to the second end of the signal electrode and each further include second ends suspended over different predetermined portions of the ground plane. In operation, one or more of the cantilevers may be actuated to move portion thereof into close proximity to the ground plane for providing one or more discrete capacitance values.

Method of forming a low cost digital variable capacitor

A capacitance coupled, transmission line-fed, radio frequency MEMS switch and its fabrication process using photoresist and other low temperature processing steps are described. The achieved switch is disposed in a low cost dielectric housing free of undesired electrical effects on the switch and on the transmission line(s) coupling the switch to an electrical circuit. The dielectric housing is provided with an array of sealable apertures useful for wet, but hydrofluoric acid-free, removal of switch fabrication employed materials and also useful during processing for controlling the operating atmosphere surrounding the switch&#x2014;e.g. at a pressure above the high vacuum level for enhanced switch damping during operation. Alternative arrangements for sealing an array of dielectric housing apertures are included. Processing details including plan and profile drawing views, specific equipment and materials identifications, temperatures and times are also disclosed.

MEMS RF switch integrated process

A method for selecting metal alloys as the electric contact materials for microelectromechanical systems (MEMS) metal contact switches. This method includes a review of alloy experience, consideration of equilibrium binary alloy phase diagrams, obtaining thin film material properties and, based on a suitable model, predicting contact electrical resistance performance. After determination of a candidate alloy material, MEMS switches are conceptualized, fabricated and tested to validate the alloy selection methodology. Minimum average contact resistance values of 1.17 and 1.87 ohms are achieved for micro-switches with gold (Au) and gold-platinum (Au-(6.3 at %)Pt) alloy contacts. In addition, 'hot-switched' life cycle test results of 1.02&#xd7;10and 2.70&#xd7;10cycles may be realized for micro-switches with Au and Au-(6.3 at %)Pt contacts. These results indicate increased wear with a small increase in contact resistance for MEMS switches with metal alloy electric contacts.

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Centerville, OH, United States of America

Kevin D Leedy