Mips Technologies, Inc.

Arm Finance Overseas Limited

Google Inc.

Bridge Crossing, LLC

Imagination Technologies Limited

Kevin D Kissell

Hartvig W J Ekner

Karagada Ramarao Kishore

Darren Miller Jones

Benjamin Charles Serebrin

Ryan C Kinter

Morten Stribaek

Georgi Beloev

Radhika Thekkath

Sanjay Vishin

Pascal Paillier

G Michael Uhler

Lawrence Henry Hudepohl

Vidya Rajagopalan

Thomas Albert Petersen

David A Courtright

Jakob Schou Jensen

Peter Koch Andersson

David Levinthal

Clinton Wills Smullen, Iv

Thomas A Petersen

Hartig W J Ekner

In one general aspect, a system includes an abstract machine instruction stream, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor is operable to generate one or more native machine instructions to explicitly control the virtual machine coprocessor.

Virtual machine coprocessor for accelerating software execution

System and method for performing a high-bandwidth memory copy. Memory transfer instructions allow for copying of data from a first memory location to a second memory location without the use of load and store word instructions thereby achieving a high-bandwidth copy. In one embodiment, the method includes the steps of (1) decoding a destination address from a first memory transfer instruction, (2) storing the destination address in a register in the bus interface unit, (3) decoding a source address from a second memory transfer instruction, and (4) copying the contents of a memory location specified by the source memory address to a memory location specified by the contents of the register. Other methods and a microprocessor system are also presented.

System and method for improving memory transfer

A method of managing processor caches. The method includes invalidating a cache line from a first instruction cache level and in response to invalidating the cache line from the first cache level, fetching data associated with the invalidated cache line from a third cache level or memory and writing the fetched data to a second cache level. The third cache level is larger or differently associative than the second cache level and the second cache level is larger or differently associative than the first cache level.

Emulating eviction data paths for invalidated instruction cache

A method of authenticating shared peripheral component interconnect express devices of a switched fabric includes associating at least one requester identifier with a physical function of a device on the switched fabric and instantiating a virtual function of the device based on the physical function. The virtual function includes the associated at least one requester identifier. The method further includes accepting memory-mapped input/output traffic through the virtual function only from a requester having a corresponding requester identifier matching an associated requester identifier of the virtual function. The method may also include allowing a write operation of the virtual function or the physical function only to an address residing within an allowable address range associated with the device.

Authenticating shared interconnect fabrics

A multiprocessor computer system includes an exception domain having multiple thread contexts (TCs) each having a restart address register, and a timer that generates a periodic interrupt request to the exception domain. The exception domain selects an eligible TC to service the interrupt request, which is non-specific regarding which TC to select. A first interrupt handler executes on the selected TC to service the interrupt request to schedule a set of processes assigned by the SMP OS for execution on the selected TC, and write an address of a second interrupt handler to the restart address register of each TC other than the selected TC. The second interrupt handler schedules a plurality of sets of processes assigned by the SMP OS for execution on respective ones of the TCs other than the selected TC.

Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor

A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.

Substituting portion of template instruction parameter with selected virtual instruction parameter

A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests. The system also includes a multiprocessor operating system (OS), configured to initially set the second control indicator to enable the VPE to service the interrupts, and further configured to schedule execution of threads on the plurality of TCs, wherein each of the threads is configured to individually disable itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator.

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by allocating context for the new thread, copying the first operand to a program counter of the new thread context, copying the second operand to a register of the new thread context, and scheduling the new thread for execution. If no new thread context is free for allocation, the microprocessor raises an exception to the fork instruction. The fork instruction is efficient because it does not copy the parent thread general purpose registers to the new thread. The second operand is typically used as a pointer to a data structure in memory containing initial general purpose register set values for the new thread.

Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on the plurality of TCs. The system also includes a multiprocessor operating system (OS), configured to schedule execution of the threads on the plurality of TCs, wherein a thread of the threads executing on one of the plurality of TCs is configured to update the shared TLB, and prior to updating the TLB to disable interrupts, to prevent the OS from unscheduling the TLB-updating thread from executing on the plurality of TCs, and disable the instruction scheduler from dispatching instructions from any of the plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.

A multithreading microprocessor has a plurality of thread contexts (TCs) each including sufficient state, such as general purpose registers and program counter, to execute a separate thread of execution as one of a plurality of symmetric processors controlled by a multiprocessor operating system. However, the microprocessor hardware does not support the ability for one TC to direct an exception to another TC, i.e., to specify to which of the other TCs the exception is directed. A first thread running on a first TC of the operating system executes architected instructions to halt a second thread (either user or kernel thread) running on a second TC, save state of the second TC, write the second TC state to emulate an exception&#x2014;including writing a restart register with the address of an exception handler, and unhalt the second TC to execute the exception hander.

Software emulation of directed exceptions in a multithreading processor

A system includes an abstract machine instruction stream, an execution trace buffer storing information to facilitate dynamic compilation, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor updates the execution trace buffer as instructions from the abstract machine instruction stream are processed. In addition, a method for facilitating dynamic compilation includes receiving an instruction to be processed, determining that the instruction marks entry into a basic block, and updating an execution trace buffer.

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Le Bar sur Loup, France

Kevin D Kissell