Xilinx, Inc.

Kevin Chung

Tetse Jang

Vi Chi Chan

Sridhar Krishnamurthy

Jason Helge Anderson

Amit Singh

Qiang Wang

Taneem Ahmed

David Nguyen Van Mau

Subodh Gupta

Mehrdad Parsa

A computer-implemented method of technology mapping a circuit design for implementation within a programmable logic device can include determining a plurality of cut sets for the circuit design, wherein each cut set includes a plurality of cuts. The method can include evaluating each cut set according to a cost function that depends, at least in part, upon a measure of inter-cut symmetry and selecting a cut set according to the cost function. Each cut of the selected cut set can represent an instantiation of at least one logic component within the programmable logic device. The circuit design specifying the selected cut set can be output.

Function symmetry-based optimization for physical synthesis of programmable integrated circuits

A computer-implemented method of implementing a circuit design that includes an initial network within a programmable logic device can include generating a first choice network from the circuit design according to a first synthesis technique and determining a placement for the first choice network. At least a second choice network can be generated from the first choice network according to a second synthesis technique. A placement for the second choice network can be determined. The placement for the first choice network can be compared with the placement for the second choice network. A placement and corresponding choice network can be selected according to the comparison, and output.

Implementation flow for electronic circuit designs using choice networks

A method and apparatus for circuit design synthesis are described. An edge flow cost function is implemented to obtain edge flow costs for nodes of a network. A subject graph of the network is then mapped using the edge flow costs.

Network mapping using edges as a parameter

An implementation of a logic description is improved. The implementation has two signals coupled to two inputs of a fanout-free cone. A swap function is determined of the inputs of the fanout-free cone. The swap function indicates whether there is a difference at an output of the fanout free cone between the fanout-free cone with and without swapping the two signals between the two inputs of the fanout-free cone. A do-not-care function of the inputs of the fanout-free cone is determined for the logic description. The do-not-care function indicates that a modification of the output of the fanout-free cone is not observable at the primary outputs of the logic description. A modified implementation of the logic description is output in response to the do-not-care function covering the swap function. The modified implementation of the logic description has the two signals swapped between the two inputs of the fanout-free cone.

Modifying a logic implementation by swapping inputs of fanout-free cones

A computer-implemented method of improving timing of a circuit design for a programmable logic device can include identifying a timing critical wire of the circuit design and determining a fanout free cone coupled to a plurality of leaf nodes, wherein the critical wire links a critical leaf node of the plurality of leaf nodes with the fanout free cone. At least one leaf node set can be selected, wherein the leaf node set includes a plurality of symmetric leaf nodes including the critical leaf node and at least one non-critical leaf node. At least two leaf nodes of a leaf node set can be swapped in the circuit design. The circuit design can be output.

Symmetry-based optimization for the physical synthesis of programmable logic devices

A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of implementations of at least one sub-circuit of the circuit design and placing the circuit design on the target IC using a primary implementation of the plurality of implementations of the sub-circuit. The primary implementation of the sub-circuit can be selectively replaced with an alternate implementation of the sub-circuit selected from the plurality of implementations of the sub-circuit. The placed circuit design, including either the primary implementation or the alternate implementation of the sub-circuit, can be output.

Implementation of alternate solutions in technology mapping and placement

Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic devices in the LUT block is determined as a function of each identified configuration bit that has a don't care condition. A dynamic power state for a subset of a second level of logic devices is determined as a function of the determined power state for the first level of logic devices. A respective value for each identified configuration bit of the LUT is selected in response to the determined dynamic power states. The respective value is placed into the design for each identified configuration bit.

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Toronto, Canada

Kevin Chung